公开(公告)号：US20160126939A1

公开(公告)日：2016-05-05

申请号：US14531419

申请日：2014-11-03

Applicant: ARM LIMITED

Inventor： Satheesh BALASUBRAMANIAN ,  James Dennis DODRILL

IPC: H03K3/3562

CPC classification number: H03K3/35625 ,  H03K3/0372

Abstract: A synchroniser flip-flop is provided, which is able to better respond to input values that are not provided for the necessary setup or hold times. The flip-flop includes a latch that includes inverter circuitry for producing a first signal and a signal in dependence on a value of an input signal at a node. A clocked inverter includes a first switch that is connected between a first reference voltage supply and an intermediate node and a second switch, which is connected between the intermediate node and a second reference voltage supply. The first switch is controlled by the first signal and the second switch is controlled by the second signal to produce an output signal at the intermediate node.

Abstract translation: 提供了同步器触发器，其能够更好地响应不为必要的建立或保持时间提供的输入值。 触发器包括锁存器，其包括用于根据节点处的输入信号的值产生第一信号和信号的反相器电路。 时钟反相器包括连接在第一参考电压源和中间节点之间的第一开关和连接在中间节点和第二参考电压源之间的第二开关。 第一开关由第一信号控制，第二开关由第二信号控制，以在中间节点产生输出信号。