公开(公告)号：US20170194046A1

公开(公告)日：2017-07-06

申请号：US14986215

申请日：2015-12-31

Applicant: ARM Limited

Inventor： Gus Yeung, JR. ,  Fakhruddin Ali Bohra ,  George Lattimore

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C8/16 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419 ,  G11C2207/2209

Abstract: Various implementations described herein may refer to and may be directed to using port modes with memory. In one implementation, a memory device may include access control circuitry used to selectively activate one of a plurality of first word-lines based on first address signals from a first access port, and used to selectively activate one of a plurality of second word-lines based on assigned address signals. The access control circuitry may include address selection circuitry configured to select the assigned address signals based on a port mode signal, where the address selection circuitry selects the first address signals as the assigned address signals when the port mode signal indicates a single port mode, and where the address selection circuitry selects second address signals from a second access port as the assigned address signals when the port mode signal indicates a dual port mode.