公开(公告)号：US09922152B2

公开(公告)日：2018-03-20

申请号：US15078824

申请日：2016-03-23

Applicant: ARM Limited

Inventor： Liangzhen Lai ,  Vikas Chandra

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A computer-implemented system and method is provided for reducing failure-in-time (FIT) errors associated with one or more sequential devices of a circuit design for a process technology. The method comprises receiving an input data file that includes register transfer level (RTL) data of the circuit design. The RTL data includes the one or more sequential devices. The method further comprises identifying a preferred logic state for each sequential device of the one or more sequential devices. The method further comprises adjusting the one or more sequential devices based on the preferred logic state.

公开(公告)号：US20170338836A1

公开(公告)日：2017-11-23

申请号：US15157814

申请日：2016-05-18

Applicant: ARM Limited

Inventor： Liangzhen Lai ,  Vikas Chandra ,  Gary Dale Carpenter

IPC: H03M13/29 ,  H03M13/27

CPC classification number: H03M13/2906 ,  H03M13/05 ,  H03M13/27 ,  H03M13/2792

Abstract: Various implementations described herein are directed to a memory device. The memory device may include a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device may include a second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code. The second interleaving circuit may interleave data bits from multiple different data words and store modified data words based on the multiple different data words.

公开(公告)号：US10122384B2

公开(公告)日：2018-11-06

申请号：US15157814

申请日：2016-05-18

Applicant: ARM Limited

Inventor： Liangzhen Lai ,  Vikas Chandra ,  Gary Dale Carpenter

IPC: G11C29/00 ,  H03M13/29 ,  H03M13/27

Abstract: Various implementations described herein are directed to a memory device. The memory device includes a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device includes a second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code. The second interleaving circuit interleaves data bits from multiple different data words and stores modified data words based on the multiple different data words.

公开(公告)号：US20170277817A1

公开(公告)日：2017-09-28

申请号：US15078824

申请日：2016-03-23

Applicant: ARM Limited

Inventor： Liangzhen Lai ,  Vikas Chandra

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A computer implemented system and method is provided for reducing failure in time (FIT) errors associated with one or more sequential devices of a circuit design for a process technology. The method comprises receiving an input data file that includes register transfer level (RTL) data of the circuit design. The RTL data includes the one or more sequential devices. The method further comprises identifying a preferred logic state for each of the one or more sequential devices. The method further comprises adjusting the one or more sequential devices based on the preferred logic state.