公开(公告)号：US10310735B2

公开(公告)日：2019-06-04

申请号：US15440254

申请日：2017-02-23

Applicant: ARM Limited

Inventor： Cédric Denis Robert Airaud ,  Max John Batley ,  Ian Michael Caulfield ,  Thomas Edward Roberts

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F12/06 ,  G06F12/02 ,  G06F12/0893

Abstract: Data storage apparatus comprises detection circuitry configured to detect a match between a multi-bit reference memory address and a test address, the test address being a combination of a multi-bit base address and a multi-bit address offset, the detection circuitry comprising: a comparator configured to compare, as a first comparison, a first subset of bits of the reference memory address with a combination of the corresponding first subset of bits of the base address and the corresponding first subset of bits of the address offset; the comparator being configured to compare, as a second comparison, a second, different subset of bits of the reference memory address with the corresponding second subset of bits of the base address; a detector configured to detect the match between the reference memory address and the test address when both of the first comparison and the second comparison detect a respective match; and control circuitry configured to control operation of the data storage apparatus in dependence upon the reference memory address when a match is detected by the detector.