公开(公告)号：US20250098326A1

公开(公告)日：2025-03-20

申请号：US18369451

申请日：2023-09-18

Applicant: ATI Technologies ULC

Inventor： Ioan CORDOS

IPC: H01L27/02 ,  H01L27/118

Abstract: Embodiments herein describe identifying voltage potentials in separate cells that can be combined so that a dummy gate between or in the cells can be removed. For example, some combinational logic cells such as XOR gates, XNOR gates, and half-adders are formed from coupling two combinational cells in sequence. Typically, a dummy gate is placed between those cells since they have different voltage potentials. However, if the cells have the same voltage potentials, then the dummy gate can be removed and the cells can overlap by sharing a net. This can reduce the overall size of the cell.