公开(公告)号：US20210158741A1

公开(公告)日：2021-05-27

申请号：US17168452

申请日：2021-02-05

Applicant: AU Optronics Corporation

Inventor： Che-Chia CHANG ,  Ming-Hsien LEE ,  Chun-Fu CHUNG ,  Ming-Hung CHUANG

IPC: G09G3/20

Abstract: A display device includes multiple shift register groups, multiple multiplexer groups, a driver IC, and multiple pixel circuits. The driver IC is configured to control the multiple shift register groups and the multiple multiplexer groups. A shift register group of the multiple shift register groups and a multiplexer group of the multiple multiplexer groups cooperatively drive a part of pixel circuits of the multiple pixel circuits. When the shift register group and the multiplexer group are enabled in a first time period, other shift register groups and other multiplexer groups are enabled in a second time period within the first time period. The first time period is longer than the second time period to render the part of pixel circuits and another part of pixel circuits to respectively have a first frame rate and a second frame rate.

公开(公告)号：US20200051486A1

公开(公告)日：2020-02-13

申请号：US16534401

申请日：2019-08-07

Applicant: AU Optronics Corporation

Inventor： Che-Chia CHANG ,  Ming-Hsien LEE ,  Chun-Fu CHUNG ,  Ming-Hung CHUANG

IPC: G09G3/20

Abstract: A display device includes multiple shift register groups, multiple multiplexer groups, a driver IC, and multiple pixel circuits. The driver IC is configured to control the multiple shift register groups and the multiple multiplexer groups. A shift register group of the multiple shift register groups and a multiplexer group of the multiple multiplexer groups cooperatively drive a part of pixel circuits of the multiple pixel circuits. When the shift register group and the multiplexer group are enabled in a first time period, other shift register groups and other multiplexer groups are enabled in a second time period within the first time period. The first time period is longer than the second time period to render the part of pixel circuits and another part of pixel circuits to respectively have a first frame rate and a second frame rate.