公开(公告)号：US20160118009A1

公开(公告)日：2016-04-28

申请号：US14644692

申请日：2015-03-11

Applicant: AU Optronics Corporation

Inventor： Chih-Lung LIN ,  Yuan-Wei DU ,  Fu-Hsing CHEN ,  Chun-Da TU

IPC: G09G3/36 ,  H03K19/0185

CPC classification number: G09G3/3677 ,  G09G3/20 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0289 ,  H03K19/018507

Abstract: A display panel includes gate lines and a gate driver. The gate driver includes series coupled driving stages, in which an N-th driving stage of the series-coupled driving stages includes a driving unit and an input control unit. The driving unit transmits a first clock signal according to a control voltage level of a control node, so as to output a gate-driving signal. The input control unit transmits the gate-driving signal outputted from an (N−1)-th driving stage to the control nodes, so as to adjust the control voltage level to one of a first voltage level and a second voltage level. A predetermined time interval is present between a rising edge of the first clock signal and a falling edge of the second clock signal. During the predetermined time interval, the control voltage level is pulled to the first voltage level by the input control unit.

Abstract translation: 显示面板包括栅极线和栅极驱动器。 栅极驱动器包括串联耦合驱动级，其中串联耦合驱动级的第N驱动级包括驱动单元和输入控制单元。 驱动单元根据控制节点的控制电压电平发送第一时钟信号，以输出栅极驱动信号。 输入控制单元将从第（N-1）驱动级输出的栅极驱动信号发送到控制节点，以将控制电压电平调整为第一电压电平和第二电压电平之一。 在第一时钟信号的上升沿和第二时钟信号的下降沿之间存在预定的时间间隔。 在预定时间间隔期间，通过输入控制单元将控制电压电平拉至第一电压电平。