公开(公告)号：US06651234B2

公开(公告)日：2003-11-18

申请号：US09985124

申请日：2001-11-01

申请人： Aarti Gupta ,  Zijiang Yang ,  Pranav Ashar ,  Sharad Malik

发明人： Aarti Gupta ,  Zijiang Yang ,  Pranav Ashar ,  Sharad Malik

IPC分类号： G06F1750

CPC分类号： G06F17/504

摘要： A method for Boolean Satisfiability (SAT). The method comprises using a variable decision heuristic in a SAT algorithm and pruning the search space of SAT using said decision heuristic. The decision heuristic is based on partitioning a conjunctive normal form (CNF) of a Boolean formula corresponding to the SAT and the partitioning is induced by a separator set. An image computaion method that uses the disclosed method for solving the SAT.

公开(公告)号：US20050149301A1

公开(公告)日：2005-07-07

申请号：US11053915

申请日：2005-02-10

申请人： Aarti Gupta ,  Pranav Ashar ,  Sharad Malik

发明人： Aarti Gupta ,  Pranav Ashar ,  Sharad Malik

IPC分类号： G06F17/10 ,  G06F17/50

CPC分类号： G06F17/5031

摘要： A method for derivation and abstraction of test models for validation of industrial designs using guided simulation is described. The method employs automatic abstractions for the test model which reduce its complexity while preserving the class of errors that can be detected by a transition tour. A method for design validation comprising generating a state-based test model of the design, abstracting said test model by retiming and latch removal; and applying validation technique on the abstracted test model. First, the number of internal (non-peripheral) latches in a design is minimized via retiming using a method of Maximal Peripheral Retiming (MPR). According to the MPR method, internal latches are retimed to the periphery of the circuit. Subsequently, all latches that can be retimed to the periphery are automatically abstracted in the test model. The validation technique may comprise of model checking, invariant checking or guided simulation using test sequences generated from the abstracted test model.

摘要翻译： 描述了使用引导模拟验证工业设计的测试模型的推导和抽象方法。 该方法对测试模型采用自动抽象，这降低了其复杂性，同时保留了过渡旅程可以检测到的错误类别。 一种用于设计验证的方法，包括生成设计的基于状态的测试模型，通过重新定时和锁定移除抽象所述测试模型; 并对抽象测试模型应用验证技术。 首先，使用最大外设重定时（MPR）的方法通过重新定时来最小化设计中的内部（非外围）锁存器的数量。 根据MPR方法，将内部锁存器重新定位到电路的周围。 随后，可以在测试模型中自动提取所有可重新定位到外围的锁存器。 验证技术可以包括模型检查，不变检查或使用从抽象测试模型生成的测试序列的引导模拟。

公开(公告)号：US06874135B2

公开(公告)日：2005-03-29

申请号：US09404599

申请日：1999-09-24

申请人： Aarti Gupta ,  Pranav Ashar ,  Sharad Malik

发明人： Aarti Gupta ,  Pranav Ashar ,  Sharad Malik

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method for derivation and abstraction of test models for validation of industrial designs using guided simulation is described. The method employs automatic abstractions for the test model which reduce its complexity while preserving the class of errors that can be detected by a transition tour. A method for design validation comprising generating a state-based test model of the design. The test model is abstracted by retiming and latch removal. Finally, a validation technique is applied on the abstracted test model. First, the number of internal (non-peripheral) latches in a design is minimized via retiming using a method of Maximal Peripheral Retiming (MPR). According to the MPR method, internal latches are retimed to the periphery of the circuit. Subsequently, all latches that can be retimed to the periphery are automatically abstracted in the test model. The validation technique may comprise of model checking, invariant checking or simulation using test sequences generated from the abstracted test model.

摘要翻译： 描述了使用引导模拟验证工业设计的测试模型的推导和抽象方法。 该方法对测试模型采用自动抽象，这降低了其复杂性，同时保留了过渡旅程可以检测到的错误类别。 一种用于设计验证的方法，包括生成设计的基于状态的测试模型。 测试模型通过重新定时和锁定去除来抽象。 最后，对抽象测试模型应用验证技术。 首先，使用最大外设重定时（MPR）的方法通过重新定时来最小化设计中的内部（非外围）锁存器的数量。 根据MPR方法，将内部锁存器重新定位到电路的周围。 随后，可以在测试模型中自动提取所有可重新定位到外围的锁存器。 验证技术可以包括模型检查，不变检查或使用从抽象测试模型生成的测试序列的模拟。

公开(公告)号：US5448497A

公开(公告)日：1995-09-05

申请号：US941658

申请日：1992-09-08

申请人： Pranav Ashar ,  Sujit Dey ,  Sharad Malik

发明人： Pranav Ashar ,  Sujit Dey ,  Sharad Malik

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A methodology for the redesign of sequential VLSI circuits to increase the circuit speed involves cascading the circuit over a plurality of time frames without the memory elements, identifying any long false paths in the cascaded circuit, reconfiguring the original circuit to eliminate the false paths while providing fanout to preserve functionality, and retiming the reconfigured circuit to reduce circuit delay.

摘要翻译： 用于重新设计用于增加电路速度的顺序VLSI电路的方法包括在多个时间帧上层叠电路而没有存储器元件，识别级联电路中的任何长假路径，重新配置原始电路以消除假路径同时提供 保留功能，并重新配置重新配置的电路以减少电路延迟。

公开(公告)号：US6038392A

公开(公告)日：2000-03-14

申请号：US85646

申请日：1998-05-27

申请人： Pranav Ashar ,  Sharad Malik ,  Margaret Martonosi ,  Peixin Zhong

发明人： Pranav Ashar ,  Sharad Malik ,  Margaret Martonosi ,  Peixin Zhong

IPC分类号： G06F9/44 ,  G06F17/10 ,  G06F17/50 ,  G06N5/04

CPC分类号： G06F17/5054

摘要： A Boolean SAT solver uses reconfigurable hardware to solve a specific input problem. Each of the plurality of ordered variables has a corresponding one of a plurality of state machines. Each state machine has an implication circuit for its respective variable, and operates in parallel according to an identical state machine. One state machine implements the Davis-Putnam method in hardware and provides improved performance over software by virtue of the parallel checking of direct and transitive implications. Another state machine implements a novel non-chronological backtracking method that takes advantage of the parallel implication checking and avoids the need to maintain or to traverse a GRASP type implication graph in the event of backtracking. The novel non-chronological backtracking provides for setting a blocking variable as a leaf variable and for changing only the value of the leaf variable, but possibly changing both the value and identity of a backtracking variable.

摘要翻译： 布尔SAT求解器使用可重构硬件来解决特定的输入问题。 多个有序变量中的每一个具有多个状态机中的对应的一个。 每个状态机具有用于其各自变量的含义电路，并且根据相同的状态机并行操作。 一个状态机通过硬件实现Davis-Putnam方法，并通过并行检查直接和传递的影响，提高了软件性能。 另一种状态机实现了一种新颖的非时间回溯方法，其利用并行含义检查的优点，并避免在回溯事件中维护或遍历GRASP类型含义图。 新颖的非时间回溯提供将阻塞变量设置为叶变量，并且仅改变叶变量的值，但可能改变回溯变量的值和身份。

公开(公告)号：US5457638A

公开(公告)日：1995-10-10

申请号：US23828

申请日：1993-02-23

申请人： Pranav Ashar ,  Sharad Malik

发明人： Pranav Ashar ,  Sharad Malik

IPC分类号： G01R31/3183 ,  G06F17/50

CPC分类号： G01R31/318357 ,  G01R31/318328 ,  G06F17/5031

摘要： A computer-implemented process for doing timing analysis of a VLSI sequential circuit that includes false paths. It includes the steps of transforming the circuit into a functionally equivalent .delta. path disjoint circuit for a given delay value and propagating all inverters to primary inputs of the circuit and performing a multifault test on all primary input fanouts of a particular length consisting solely either of all zoroes or of all ones.

摘要翻译： 用于对包括假路径的VLSI时序电路进行定时分析的计算机实现的过程。 它包括以下步骤：将电路转换成用于给定延迟值的功能等效的三角洲路径不相交电路，并将所有逆变器传播到电路的主输入端，并且对所有主要输入扇区执行多个测试，所述主要输入扇出仅包括所有 zoroes或所有的。

公开(公告)号：US06247164B1

公开(公告)日：2001-06-12

申请号：US08919282

申请日：1997-08-28

申请人： Pranav Ashar ,  Sharad Malik ,  Margaret Martonosi ,  Peixin Zhong

发明人： Pranav Ashar ,  Sharad Malik ,  Margaret Martonosi ,  Peixin Zhong

IPC分类号： G06F1750

CPC分类号： G06F17/504

摘要： Disclosed is a configurable hardware system and method for implementing instance-specific (per-formula) SAT-solver circuits. A template design is provided for producing these circuits on a per-formula basis. The typical hardware requirements for implementing the invention makes the design amenable to current or next-generation FPGA implementation. Hardware simulations indicate that for many difficult SAT problems, the system according to the invention can offer one to three orders of magnitude speedup over prior art software implementations.

摘要翻译： 公开了用于实现实例特定（每公式）SAT解算器电路的可配置硬件系统和方法。 提供了一个模板设计，用于在每个公式的基础上产生这些电路。 实现本发明的典型硬件要求使得设计适合当前或下一代FPGA实现。 硬件模拟表明，对于许多困难的SAT问题，根据本发明的系统可以提供超过现有技术的软件实现一到三个数量级的加速。

公开(公告)号：US6035109A

公开(公告)日：2000-03-07

申请号：US847952

申请日：1997-04-22

申请人： Pranav N Ashar ,  Aarti Gupta ,  Sharad Malik

发明人： Pranav N Ashar ,  Aarti Gupta ,  Sharad Malik

IPC分类号： G06F17/50 ,  G06F17/00

CPC分类号： G06F17/504

摘要： The Complete-1-Distinguishability (C-1-D) property is used for simplifying FSM verification. This property eliminates the need for a traversal of the product machine for the implementation machine and the specification machine. Instead, a much simpler check suffices. This check consists of first obtaining a 1-equivalence mapping between the states of the two machines, and then checking that it is a bisimulation relation. The C-1-D property can be used directly on specifications for which it naturally holds. This property can be enforced on arbitrary FSMs by exposing some of the latch outputs as pseudo-primary outputs during synthesis and verification. In this sense, the synthesis/verification methodology provides another point in the tradeoff curve between constraints-on-synthesis versus complexity-of-verification.

摘要翻译： 完整的1分辨率（C-1-D）属性用于简化FSM验证。 该特性不需要对实施机器和规格机器的产品机器进行遍历。 相反，一个更简单的检查就足够了。 该检查包括首先在两台机器的状态之间获得1等效映射，然后检查它是否是双向关系。 C-1-D属性可以直接用于其自然拥有的规格。 通过在合成和验证期间将某些锁存输出作为伪主输出，可以在任意的FSM上强制实现该属性。 在这个意义上，综合/验证方法在合成约束与验证复杂度之间的权衡曲线中提供了另一个要点。

公开(公告)号：US06442743B1

公开(公告)日：2002-08-27

申请号：US09097107

申请日：1998-06-12

申请人： Majid Sarrafzadeh ,  Lawrence Pileggi ,  Sharad Malik ,  Feroze Peshotan Taraporevala ,  Abhijeet Chakraborty ,  Gary K. Yeap ,  Salil R. Raje ,  Lilly Shieh ,  Douglas B. Boyle ,  Dennis Yamamoto

发明人： Majid Sarrafzadeh ,  Lawrence Pileggi ,  Sharad Malik ,  Feroze Peshotan Taraporevala ,  Abhijeet Chakraborty ,  Gary K. Yeap ,  Salil R. Raje ,  Lilly Shieh ,  Douglas B. Boyle ,  Dennis Yamamoto

IPC分类号： G06F1750

CPC分类号： G06F17/5072

摘要： The disclosure describes a placement method for the physical design of integrated circuits in which natural topological feature clusters are discovered and exploited during the placement process is disclosed. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. An iterative placement refinement process is done using a technique referred to as Dual Geometrically-Bounded FM (GBFM). GBFM is applied on a local basis to windows encompassing a number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region stops participating. Following the foregoing global placement process the circuit is then ready for detailed placement in which cells are assigned to placement rows.

摘要翻译： 本公开描述了用于集成电路的物理设计的放置方法，其中公开了在放置过程期间发现和利用自然拓扑特征簇。 拓扑群集驱动初始位置，其中所有的拓扑群集的门最初都放置在放置布局的一个bin或一组位置相关的区域中。 使用称为双重几何限幅FM（GBFM）的技术完成迭代放置细化过程。 GBFM在本地基础上应用于包含多个分区的窗口。 从迭代到迭代，窗口可能会改变位置并且大小变化。 当由窗口界定的区域在指定的成本函数方面满足指定的成本阈值时，该区域停止参与。 按照上述全局放置过程，电路准备好进行详细的放置，其中将单元格分配给放置行。

公开(公告)号：US5841673A

公开(公告)日：1998-11-24

申请号：US593569

申请日：1996-01-30

申请人： Noriya Kobayashi ,  Sharad Malik

发明人： Noriya Kobayashi ,  Sharad Malik

IPC分类号： G06F17/50 ,  G06F17/00

CPC分类号： G06F17/5031

摘要： A delay network of logic circuit delay data composed of a first set of vertices containing first to fourth vertices, and a first set of weighted directional edges containing a first directional edge extending from the first vertex to the fourth vertex, a second directional edge extending from the second vertex to the third vertex, a third directional edge extending from the first vertex to the third vertex, and a fourth directional edge extending from the second vertex to the fourth vertex, is converted into a delay network composed of a second set of vertices containing the first to fourth vertices and an added fifth vertex, and a second set of weighted directional edges containing a fifth directional edge extending from the first vertex to the fifth vertex, a sixth directional edge extending from the second vertex to the fifth vertex, a seventh directional edge extending from the fifth vertex to the third vertex, and an eighth directional edge extending from the fifth vertex to the fourth vertex.

摘要翻译： 由包含第一至第四顶点的第一组顶点组成的逻辑电路延迟数据的延迟网络以及包含从第一顶点延伸到第四顶点的第一方向边缘的第一组加权方向边缘，第二方向边缘从 第二顶点到第三顶点，从第一顶点延伸到第三顶点的第三方向边缘和从第二顶点延伸到第四顶点的第四方向边缘被转换成由第二组顶点组成的延迟网络 包含第一至第四顶点和第五顶点，以及包含从第一顶点延伸到第五顶点的第五方向边缘的第二组加权方向边缘，从第二顶点延伸到第五顶点的第六方向边缘， 从第五顶点延伸到第三顶点的第七方向边缘以及从第五顶点延伸到f的第八方向边缘 神话顶点