公开(公告)号：US10601421B1

公开(公告)日：2020-03-24

申请号：US16557201

申请日：2019-08-30

Applicant: Ademco Inc.

Inventor： Jesus Omar Ponce ,  Luis Carlos Murillo ,  Cesar Alejandro Arzate ,  Eduardo Saenz Balderrama

IPC: H03K19/0175 ,  F24F11/88

Abstract: A circuit to isolate a first circuit node from second circuit node at certain times yet connect the first circuit node and second circuit node at other times. For example, the isolation circuit may isolate a reference node from a system ground during certain phases of operation, but temporarily connect the reference node to the system ground during other phases. An isolation circuit of this disclosure may include a pair of MOSFETs in a back-to-back connection. The MOSFETs may be placed between the two nodes to be isolated. The MOSFETS may be driven by a bipolar junction transistor (BJT). A control signal applied to the BJT emitter controls the operation of the pair of MOSFETs. The isolation or connection from the power supply reference node to system ground may be controlled by applying a HIGH or LOW logic signal to the PNP transistor emitter.