公开(公告)号：US07450594B2

公开(公告)日：2008-11-11

申请号：US10042441

申请日：2001-11-09

申请人： Akira Yamamori ,  Takeshi Sasaki ,  Eiji Maeda ,  Masao Maeda ,  Tatsuya Oku ,  Yoshinori Okuda ,  Tsuguo Okada ,  Akihiro Yasuo ,  Jinichi Yoshizawa

发明人： Akira Yamamori ,  Takeshi Sasaki ,  Eiji Maeda ,  Masao Maeda ,  Tatsuya Oku ,  Yoshinori Okuda ,  Tsuguo Okada ,  Akihiro Yasuo ,  Jinichi Yoshizawa

IPC分类号： H04L12/56

CPC分类号： H04Q11/0478 ,  H04L2012/5605 ,  H04L2012/561 ,  H04L2012/5658 ,  H04L2012/5662

摘要： In multi-connections, a message writing apparatus is provided. This message writing apparatus (21) comprises a path recognizing section (21a), a received message assembling section (21b), a receive control section (21c), an arbitrating section (21d) and an external memory control section (21e). When a received ATM cell is written/readout in/from a receiving buffer, it is written/read out in a memory area corresponding to each path, which enables the processing of AAL5 messages from a plurality of paths and improves the transfer processing capability, thereby leading to realizing a shortening of the data transfer time.

摘要翻译： 在多连接中，提供消息写入装置。 该消息写入装置（21）包括路径识别部分（21a），接收消息组合部分（21b），接收控制部分（21c），仲裁部分（21d）和外部存储器控制部分 21 e）。 当接收到的ATM信元在接收缓冲器中进行写入/读出时，在与各路径相对应的存储区域中写入/读出，能够对来自多个路径的AAL5消息进行处理，提高传送处理能力， 从而实现数据传送时间的缩短。

公开(公告)号：US08321715B2

公开(公告)日：2012-11-27

申请号：US12368715

申请日：2009-02-10

申请人： Tatsuya Oku ,  Masato Hashizume ,  Hiroshi Nishida

发明人： Tatsuya Oku ,  Masato Hashizume ,  Hiroshi Nishida

IPC分类号： G06F1/00

CPC分类号： G06F1/12

摘要： A communication apparatus having a clock interface unit supplying a clock signal for synchronization, includes a clock extracting section for extracting a clock component from a receive signal, a decoding section for generating a decoded signal by decoding in a predetermined encoding form the clock component extracted by the clock extracting section, a frame converting section for creating a receive frame by converting the decoded signal to a frame in a predetermined frame form, a determining section for determining whether the predetermined encoding form and the predetermined frame form are right or not on a basis of the receive frame, a setting section for performing setting regarding the clock signal on a basis of the encoding form and frame form determined to be right by the determining section, and a clock signal output section for outputting the clock signal generated on a basis of the setting by the setting section.

摘要翻译： 具有提供用于同步的时钟信号的时钟接口单元的通信装置包括：时钟提取部分，用于从接收信号中提取时钟分量;解码部分，用于通过以预定的编码形式解码解码信号，由时钟分量提取时钟分量， 时钟提取部分，用于通过将解码信号转换为预定帧形式的帧来创建接收帧的帧转换部分，用于基于所述确定部分确定预定编码形式和预定帧形式是否是正确的 一个设置部分，用于根据由确定部分确定为正确的编码形式和帧形式来执行关于时钟信号的设置;以及时钟信号输出部分，用于输出基于 由设置部分设置。

公开(公告)号：US20090249107A1

公开(公告)日：2009-10-01

申请号：US12368715

申请日：2009-02-10

申请人： Tatsuya Oku ,  Masato Hashizume ,  Hiroshi Nishida

发明人： Tatsuya Oku ,  Masato Hashizume ,  Hiroshi Nishida

IPC分类号： G06F1/12

CPC分类号： G06F1/12

摘要： A communication apparatus having a clock interface unit supplying a clock signal for synchronization, includes a clock extracting section for extracting a clock component from a receive signal, a decoding section for generating a decoded signal by decoding in a predetermined encoding form the clock component extracted by the clock extracting section, a frame converting section for creating a receive frame by converting the decoded signal to a frame in a predetermined frame form, a determining section for determining whether the predetermined encoding form and the predetermined frame form are right or not on a basis of the receive frame, a setting section for performing setting regarding the clock signal on a basis of the encoding form and frame form determined to be right by the determining section, and a clock signal output section for outputting the clock signal generated on a basis of the setting by the setting section.

摘要翻译： 具有提供用于同步的时钟信号的时钟接口单元的通信装置包括：时钟提取部分，用于从接收信号中提取时钟分量;解码部分，用于通过以预定的编码形式解码解码信号，由时钟分量提取时钟分量， 时钟提取部分，用于通过将解码信号转换为预定帧形式的帧来创建接收帧的帧转换部分，用于基于所述确定部分确定预定编码形式和预定帧形式是否是正确的 一个设置部分，用于根据由确定部分确定为正确的编码形式和帧形式来执行关于时钟信号的设置;以及时钟信号输出部分，用于输出基于 由设置部分设置。

公开(公告)号：US08184665B2

公开(公告)日：2012-05-22

申请号：US12627017

申请日：2009-11-30

申请人： Tatsuya Oku ,  Yasuo Takami ,  Masato Hashizume

发明人： Tatsuya Oku ,  Yasuo Takami ,  Masato Hashizume

IPC分类号： H04J3/06

CPC分类号： H04J3/0688 ,  H04J3/0691 ,  H04J3/0697 ,  H04J2203/006

摘要： A disclosed network device includes a plurality of interface cards that receive clock signals and clock signal quality information from other devices via communication lines, respectively being predetermined communication line types corresponding to the plurality of interface cards, a controller that acquires the clock signal quality information and determines one of the clock signals having a highest quality based on this, and a clock processor that generates a synchronization clock signal used for network synchronization the clock processor, based on the determined one of the clock signals, whereby the clock processor includes a frequency measuring instrument that measures a frequency component of the one of the clock signals, and determines the communication line type corresponding to one of the interface cards, and a clock controller that provides a coefficient to a digital filter based on the determined communication line type.

摘要翻译： 所公开的网络设备包括多个接口卡，其经由通信线路从其他设备接收时钟信号和时钟信号质量信息，分别是对应于多个接口卡的预定通信线路类型，获取时钟信号质量信息的控制器和 基于此确定具有最高质量的时钟信号中的一个;以及时钟处理器，其基于所确定的一个时钟信号，生成用于网络同步时钟处理器的同步时钟信号，由此时钟处理器包括频率测量 测量时钟信号之一的频率分量的仪器，并确定与一个接口卡相对应的通信线路类型;以及时钟控制器，其基于所确定的通信线路类型向数字滤波器提供系数。

公开(公告)号：US07027459B2

公开(公告)日：2006-04-11

申请号：US10083997

申请日：2002-02-25

申请人： Satoshi Fukui ,  Tatsuya Oku ,  Kenji Fukunaga

发明人： Satoshi Fukui ,  Tatsuya Oku ,  Kenji Fukunaga

IPC分类号： H04L12/56

CPC分类号： H04Q11/0478 ,  H04L2012/561 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672

摘要： Printed circuit boards 11 to 11n are connected in a star-like configuration with a single packet processing IC 42, connected to a CPU 41, at its center, each printed circuit board being connected to the packet processing IC by a high-speed supervisory control line 21 having a sufficient transmission capacity to transfer therethrough transparent information and alarm transfer information as well as information from the central processing unit in packet form, and the transparent information and the alarm transfer information are communicated between the printed circuit boards via the high-speed supervisory control line and via the packet processing IC, with provisions made for the packet processing IC to detect a destination from the packet information received from the originating printed circuit board and to transmit the packet information to the terminating printed circuit board. Further, provisions are made to transmit packetized cells to the terminating printed circuit board in accordance with time priority, thereby achieving a transmission line terminating apparatus with a reduced number of wiring lines.

摘要翻译： 印刷电路板11至11n以星形结构连接到单个分组处理IC 42，其连接到CPU 41，在其中心，每个印刷电路板通过高速监视连接到分组处理IC 控制线路21具有足够的传输容量以通过透明信息和报警传送信息以及来自中央处理单元的分组形式的信息传输，并且透明信息和报警传送信息通过高速传输信息在印刷电路板之间传送， 通过分组处理IC，对分组处理IC进行规定，从从始发印刷电路板接收的分组信息中检测目的地，并将分组信息发送到终止印刷电路板。 此外，根据时间优先，进行分组化的小区发送到终端印刷电路板，从而实现布线数量减少的传输线路终端装置。

公开(公告)号：US5857092A

公开(公告)日：1999-01-05

申请号：US634430

申请日：1996-04-18

申请人： Yoshinori Nakamura ,  Tatsuya Oku ,  Miki Hagino ,  Nobuo Iguchi ,  Hiroaki Mori ,  Yuuki Tsuji

发明人： Yoshinori Nakamura ,  Tatsuya Oku ,  Miki Hagino ,  Nobuo Iguchi ,  Hiroaki Mori ,  Yuuki Tsuji

IPC分类号： H04J3/00 ,  H04J3/16 ,  H04L29/06 ,  G06F15/16

CPC分类号： H04J3/1611 ,  Y10S370/907

摘要： An interface apparatus for SDH/SONET interconnection includes a transmission interface section provided at a position where an apparatus of the SDH system and an apparatus of the SONET system face each other and adapted to transmit a signal toward an apparatus of a different system. The interface apparatus for SDH/SONET interconnection further includes a mode setting unit for setting a mode suitable for an apparatus of a counterpart system, a frame synchronization information inserting unit provided in the transmission interface section and adapted to insert frame synchronization information corresponding to the mode set by the mode setting unit, and an overhead information inserting unit provided in the transmission interface section and adapted to insert overhead information corresponding to the mode set by the mode setting unit. This structure makes is possible to easily interconnect apparatuses of different systems (apparatuses of the SDH system and the SONET system) so as to operate them.

摘要翻译： 用于SDH / SONET互连的接口装置包括：传输接口部分，设置在SDH系统的装置和SO​​NET系统的装置相对的位置，并适于向不同系统的装置发送信号。 用于SDH / SONET互连的接口装置还包括用于设置适合于对方系统的装置的模式的模式设置单元，设置在传输接口部分中的帧同步信息插入单元，并适于插入对应于模式的帧同步信息 由所述模式设定单元设定的开销信息插入单元，以及设置在所述发送接口单元中的开销信息插入单元，用于插入与所述模式设定单元设定的模式对应的开销信息。 这种结构使得可以容易地互连不同系统的设备（SDH系统和SONET系统的设备）以便操作它们。