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1.发明授权Method and apparatus for releasing functional units in a multithreaded VLIW processor 有权用于释放多线程VLIW处理器中的功能单元的方法和装置公开(公告)号：US06665791B1
公开(公告)日：2003-12-16
申请号：US09538669
申请日：2000-03-30
IPC分类号： G06F15163
CPC分类号： G06F9/3851 , G06F9/3853
摘要： A method and apparatus are disclosed for releasing functional units in a multithreaded very large instruction word (VLIW) processor. The functional unit release mechanism can retrieve the capacity lost due to multiple cycle instructions. The functional unit release mechanism of the present invention permits idle functional units to be reallocated to other threads, thereby improving workload efficiency. Instruction packets are assigned to functional units, which can maintain their state, independent of the issue logic. Each functional unit has an associated state machine (SM) that keeps track of the number of cycles that the functional unit will be occupied by a multiple-cycle instruction. Functional units do not reassign themselves as long as the functional unit is busy. When the instruction is complete, the functional unit can participate in functional unit allocation, even if other functional units assigned to the same thread are still busy. The functional unit release approach of the present invention allows the functional units that are not associated with a multiple-cycle instruction to be allocated to other threads while the blocked thread is waiting, thereby improving throughput of the multithreaded VLIW processor. Since the state is associated with each functional unit separately from the instruction issue unit, the functional units can be assigned to threads independently of the state of any one thread and its constituent instructions.
摘要翻译： 公开了用于释放多线程超大指令字（VLIW）处理器中的功能单元的方法和装置。 功能单元释放机构可以检索由于多个循环指令而导致的容量损失。 本发明的功能单元释放机构允许将空闲功能单元重新分配给其他线程，从而提高工作效率。 指令包被分配给功能单元，它们可以保持其状态，而与发行逻辑无关。 每个功能单元具有关联的状态机（SM），其跟踪功能单元将被多周期指令占用的周期数。 只要功能单元繁忙，功能单元就不会自动重新分配。 指令完成后，即使分配给同一线程的其他功能单元仍然忙，功能单元也可以参与功能单元分配。 本发明的功能单元释放方法允许在阻塞的线程等待时将不与多周期指令相关联的功能单元分配给其他线程，从而提高多线程VLIW处理器的吞吐量。 由于状态与指令发布单元分开地与每个功能单元相关联，所以功能单元可以独立于任何一个线程的状态及其组成指令分配给线程。
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2.发明授权Method and apparatus for allocating functional units in a multithreaded VLIW processor 失效用于在多线程VLIW处理器中分配功能单元的方法和装置公开(公告)号：US07007153B1
公开(公告)日：2006-02-28
申请号：US09538670
申请日：2000-03-30
CPC分类号： G06F9/3851 , G06F9/3853
摘要： A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional VLIW architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes a compiler to detect parallelism. The disclosed multithreaded VLIW architecture exploits program parallelism by issuing multiple instructions, in a similar manner to single threaded VLIW processors, from a single program sequencer, and also supports multiple program sequencers, as in simultaneous multithreading. Instructions are allocated to functional units to issue multiple VLIW instructions to multiple functional units in the same cycle. The allocation mechanism of the present invention occupies a pipeline stage just before arguments are dispatched to functional units. The allocate stage determines how to group the instructions together to maximize efficiency, by selecting appropriate instructions and assigning the instructions to the FUs. The criteria for selection are thread priority or resource availability or both. Under the thread priority criteria, different threads can have different priorities. The allocate stage selects and forwards the packets (or instructions from packets) for execution belonging to the thread with the highest priority according to the priority policy implemented. Under the resource availability criteria, a packet (having up to K instructions) can be allocated only if the resources (functional units) required by the packet are available for the next cycle. Functional units report their availability to the allocate stage.
摘要翻译： 公开了用于在多线程超大指令字（VLIW）处理器中分配功能单元的方法和装置。 本发明结合了常规VLIW架构和常规多线程体系结构的技术，以减少单个程序内的执行时间，以及跨工作负载。 本发明利用编译器来检测并行性。 所公开的多线程VLIW架构通过从单个程序定序器以类似于单线程VLIW处理器的方式发出多个指令来利用程序并行性，并且还支持多个程序定序器，如同时多线程。 指令分配给功能单元，以在同一周期内向多个功能单元发出多个VLIW指令。 本发明的分配机制在将参数分派到功能单元之前占据了流水线阶段。 分配阶段通过选择适当的指令并将指令分配给FU来确定如何将指令组合在一起以最大化效率。 选择的标准是线程优先级或资源可用性或两者。 在线程优先级标准下，不同的线程可以有不同的优先级。 分配阶段根据实现的优先级策略，选择并转发属于具有最高优先级的线程的数据包（或数据包的指令）。 在资源可用性标准下，仅当分组所需的资源（功能单元）可用于下一个周期时，才能分配（具有高达K个指令）的分组。 功能单位向分配阶段报告其可用性。
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3.发明授权Method and apparatus for splitting packets in multithreaded VLIW processor 有权用于在多线程VLIW处理器中分组数据包的方法和装置公开(公告)号：US07096343B1
公开(公告)日：2006-08-22
申请号：US09538755
申请日：2000-03-30
IPC分类号： G06F9/50
CPC分类号： G06F9/3853 , G06F9/3851 , G06F9/3885
摘要： A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded architectures. Instruction packet splitting allows an instruction bundle to be partially issued in one cycle, with the remainder of the bundle issued during a subsequent cycle. The allocation hardware assigns as many instructions from each packet as will fit on the available functional units, rather than allocating all instructions in an instruction packet at one time. Those instructions that cannot be allocated to a functional unit are retained in a ready-to-run register. On subsequent cycles, instruction packets in which all instructions have been issued to functional units are updated from their thread's instruction stream, while instruction packets with instructions that have been held are retained. The functional unit allocation logic can then assign instructions from the newly-loaded instruction packets as well as instructions that were not issued from the retained instruction packets.
摘要翻译： 公开了用于在多线程超大指令字（VLIW）处理器中分配功能单元的方法和装置。 本发明结合了传统的非常长的指令字架构和传统的多线程体系结构的技术，以减少单个程序内的执行时间以及跨工作负载。 本发明利用指令分组分解来恢复传统多线程体系结构损失的一些效率。 指令包分割允许在一个周期内部分地发出指令包，在后续周期中发出捆绑的剩余部分。 分配硬件分配来自每个分组的指令将适合可用的功能单元，而不是一次分配指令分组中的所有指令。 那些不能分配给功能单元的指令被保留在一个准备运行的寄存器中。 在随后的周期中，已经从其线程的指令流更新了向功能单元发出了所有指令的指令包，同时保留了具有指令的指令包。 然后，功能单元分配逻辑可以从新加载的指令分组以及未从保留的指令分组发出的指令分配指令。
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4.发明授权Method and apparatus for identifying splittable packets in a multithreaded VLIW processor 有权用于在多线程VLIW处理器中识别可分页分组的方法和装置公开(公告)号：US06658551B1
公开(公告)日：2003-12-02
申请号：US09538757
申请日：2000-03-30
IPC分类号： G06F900
CPC分类号： G06F9/3885 , G06F9/3851 , G06F9/3853
摘要： A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word (VLIW) architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded architectures. Instruction packet splitting allows an instruction bundle to be partially issued in one cycle, with the remainder of the bundle issued during a subsequent cycle. There are times, however, when instruction packets cannot be split without violating the semantics of the instruction packet assembled by the compiler. A packet split identification bit is disclosed that allows hardware to efficiently determine when it is permissible to split an instruction packet. The split bit informs the hardware when splitting is prohibited. The allocation hardware assigns as many instructions from each packet as will fit on the available functional units, rather than allocating all instructions in an instruction packet at one time, provided the split bit has not been set. Those instructions that cannot be allocated to a functional units are retained in a ready-to-run register. On subsequent cycles, instruction packets in which all instructions have been issued to functional units are updated from their thread's instruction stream, while instruction packets with instructions that have been held are retained. The functional unit allocation logic can then assign instructions from the newly-loaded instruction packets as well as instructions that were not issued from the retained instruction packets.
摘要翻译： 公开了用于在多线程超大指令字（VLIW）处理器中分配功能单元的方法和装置。 本发明结合了传统的非常长的指令字（VLIW）架构和常规多线程体系结构的技术，以减少单个程序内的执行时间，以及跨工作负载。 本发明利用指令分组分解来恢复传统多线程体系结构损失的一些效率。 指令包分割允许在一个周期内部分地发出指令包，在后续周期中发出捆绑的剩余部分。 然而，有时候，当指令包不能被分割而不违反编译器组装的指令包的语义时， 公开了一种分组分割识别位，其允许硬件有效地确定何时可以分割指令分组。 拆分时禁止拆分硬件。 分配硬件分配来自每个分组的指令将适合可用的功能单元，而不是一次分配指令分组中的所有指令，前提是分裂位尚未设置。 那些不能分配给功能单元的指令将保留在一个即可运行的寄存器中。 在随后的周期中，已经从其线程的指令流更新了向功能单元发出了所有指令的指令包，同时保留了具有指令的指令包。 然后，功能单元分配逻辑可以从新加载的指令分组以及未从保留的指令分组发出的指令分配指令。
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公开(公告)号：US20070219936A1
公开(公告)日：2007-09-20
申请号：US11539350
申请日：2006-10-06
IPC分类号： G06F17/00
CPC分类号： G11B20/10 , G11B2020/10537 , G11B2020/10759 , G11B2220/2516 , H04L69/22 , H04L2012/2849
摘要： A method includes storing first and second sets of parameters in a register. Each set of parameters defines a storage transaction to store data to a computer readable medium or a retrieval transaction to retrieve data from the computer readable medium. The first storage or retrieval transaction is performed according to the first set of parameters. The second set of parameters is retrieved from the register automatically when the first storage or retrieval transaction is completed, without waiting for a further command from a control processor. The second storage or retrieval transaction is performed according to the retrieved second set of parameters. A system for performing the method and a computer readable medium containing pseudocode for generating an application specific integrated circuit that performs the method are provided.
摘要翻译： 一种方法包括将第一和第二组参数存储在寄存器中。 每组参数定义存储事务以将数据存储到计算机可读介质或检索事务以从计算机可读介质检索数据。 根据第一组参数执行第一个存储或检索事务。 当第一个存储或检索事务完成时，自动从寄存器中检索第二组参数，而不用等待来自控制处理器的进一步命令。 根据检索的第二组参数来执行第二存储或检索事务。 提供一种用于执行该方法的系统和包含用于生成执行该方法的专用集成电路的伪代码的计算机可读介质。
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公开(公告)号：US07299338B2
公开(公告)日：2007-11-20
申请号：US10722100
申请日：2003-11-25
申请人： Rainer Buchty , Nevin Heintze , Dino P. Oliva
发明人： Rainer Buchty , Nevin Heintze , Dino P. Oliva
IPC分类号： G06F12/04
CPC分类号： G06F9/355 , G06F9/30036 , G06F9/3004 , G06F9/30189 , G06F9/345
摘要： Disclosed is a vector indexed memory unit and method of operation. In one embodiment a plurality of values are stored in segments of a vector index register. Individual ones of the values are provided to an associated operator (e.g., adder or bit replacement). Individual ones of the operators operates on its associated vector index value and a base value to generate a memory address. These memory addresses are then concurrently accessed in one or more memory units. If the data in the memory units are organized as data tables, the apparatus allows for multiple concurrent table lookups. In an alternate embodiment, in addition to the above described operators generating multiple memory addresses, an adder is provided to add the base value to the value represented by the concatenation of the bits in the vector index register to generate a single memory address. Multiplexers controlled by a programmable mode select signal are used to provide either the multiple memory addresses or the single memory address to the memory units. This alternate embodiment provides an apparatus that can programmably function in either an vector indexed memory mode or a conventional memory addressing mode.
摘要翻译： 公开了一种向量索引记忆单元和操作方法。 在一个实施例中，多个值被存储在矢量索引寄存器的段中。 将各个值提供给相关联的运算符（例如，加法器或位替换）。 运营商中的各个运营商根据其相关的向量索引值和基本值来生成内存地址。 这些存储器地址然后在一个或多个存储器单元中同时访问。 如果存储单元中的数据被组织为数据表，则该设备允许多个并发表查找。 在替代实施例中，除了上述描述的生成多个存储器地址的操作器之外，提供加法器以将基本值添加到由向量索引寄存器中的位的级联表示的值以生成单个存储器地址。 由可编程模式选择信号控制的多路复用器用于向存储器单元提供多个存储器地址或单个存储器地址。 该替代实施例提供了一种可编程地在矢量索引存储器模式或常规存储器寻址模式中工作的装置。
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公开(公告)号：US07577819B2
公开(公告)日：2009-08-18
申请号：US11973078
申请日：2007-10-05
申请人： Rainer Buchty , Nevin Heintze , Dino P. Oliva
发明人： Rainer Buchty , Nevin Heintze , Dino P. Oliva
CPC分类号： G06F9/355 , G06F9/30036 , G06F9/3004 , G06F9/30189 , G06F9/345
摘要： Disclosed is a vector indexed memory unit and method of operation. In one embodiment a plurality of values are stored in segments of a vector index register. Individual ones of the values are provided to an associated operator (e.g., adder or bit replacement). Individual ones of the operators operates on its associated vector index value and a base value to generate a memory address. These memory addresses are then concurrently accessed in one or more memory units. If the data in the memory units are organized as data tables, the apparatus allows for multiple concurrent table lookups. In an alternate embodiment, in addition to the above described operators generating multiple memory addresses, an adder is provided to add the base value to the value represented by the concatenation of the bits in the vector index register to generate a single memory address. Multiplexers controlled by a programmable mode select signal are used to provide either the multiple memory addresses or the single memory address to the memory units. This alternate embodiment provides an apparatus that can programmably function in either an vector indexed memory mode or a conventional memory addressing mode.
摘要翻译： 公开了一种向量索引记忆单元和操作方法。 在一个实施例中，多个值被存储在矢量索引寄存器的段中。 将各个值提供给相关联的运算符（例如，加法器或位替换）。 运营商中的各个运营商根据其相关的向量索引值和基本值来生成内存地址。 这些存储器地址然后在一个或多个存储器单元中同时访问。 如果存储单元中的数据被组织为数据表，则该设备允许多个并发表查找。 在替代实施例中，除了上述描述的生成多个存储器地址的操作器之外，提供加法器以将基本值添加到由向量索引寄存器中的位的级联表示的值以生成单个存储器地址。 由可编程模式选择信号控制的多路复用器用于向存储器单元提供多个存储器地址或单个存储器地址。 该替代实施例提供了一种可编程地在矢量索引存储器模式或常规存储器寻址模式中工作的装置。
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公开(公告)号：US20070195957A1
公开(公告)日：2007-08-23
申请号：US11539327
申请日：2006-10-06
IPC分类号： H04L9/00
CPC分类号： G06F21/72 , H04L9/0894 , H04L2209/603
摘要： In a system having a control processor, an apparatus is provided with at least one memory. The at least one memory includes a first memory portion for storing at least one first decryption key. A decryption engine uses the first decryption key to decrypt information. A key processor provides the first decryption key to the decryption engine without allowing the control processor to access the first decryption key. A system incorporating the key processing apparatus and a method of using the apparatus are also provided.
摘要翻译： 在具有控制处理器的系统中，设备具有至少一个存储器。 所述至少一个存储器包括用于存储至少一个第一解密密钥的第一存储器部分。 解密引擎使用第一解密密钥来解密信息。 密钥处理器向解密引擎提供第一解密密钥，而不允许控制处理器访问第一解密密钥。 还提供了一种结合密钥处理装置的系统和使用该装置的方法。
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公开(公告)号：US20080104364A1
公开(公告)日：2008-05-01
申请号：US11973078
申请日：2007-10-05
申请人： Rainer Buchty , Nevin Heintze , Dino Oliva
发明人： Rainer Buchty , Nevin Heintze , Dino Oliva
IPC分类号： G06F12/04
CPC分类号： G06F9/355 , G06F9/30036 , G06F9/3004 , G06F9/30189 , G06F9/345
摘要： Disclosed is a vector indexed memory unit and method of operation. In one embodiment a plurality of values are stored in segments of a vector index register. Individual ones of the values are provided to an associated operator (e.g., adder or bit replacement). Individual ones of the operators operates on its associated vector index value and a base value to generate a memory address. These memory addresses are then concurrently accessed in one or more memory units. If the data in the memory units are organized as data tables, the apparatus allows for multiple concurrent table lookups. In an alternate embodiment, in addition to the above described operators generating multiple memory addresses, an adder is provided to add the base value to the value represented by the concatenation of the bits in the vector index register to generate a single memory address. Multiplexers controlled by a programmable mode select signal are used to provide either the multiple memory addresses or the single memory address to the memory units. This alternate embodiment provides an apparatus that can programmably function in either an vector indexed memory mode or a conventional memory addressing mode.
摘要翻译： 公开了一种向量索引记忆单元和操作方法。 在一个实施例中，多个值被存储在矢量索引寄存器的段中。 将各个值提供给相关联的运算符（例如，加法器或位替换）。 运营商中的各个运营商根据其相关的向量索引值和基本值来生成内存地址。 这些存储器地址然后在一个或多个存储器单元中同时访问。 如果存储单元中的数据被组织为数据表，则该设备允许多个并发表查找。 在替代实施例中，除了上述描述的生成多个存储器地址的操作器之外，提供加法器以将基本值添加到由向量索引寄存器中的位的级联表示的值以生成单个存储器地址。 由可编程模式选择信号控制的多路复用器用于向存储器单元提供多个存储器地址或单个存储器地址。 该替代实施例提供了一种可编程地在矢量索引存储器模式或常规存储器寻址模式中工作的装置。
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公开(公告)号：US20070058633A1
公开(公告)日：2007-03-15
申请号：US11226507
申请日：2005-09-13
申请人： Jian-Guo Chen , Nevin Heintze , Hakan Pekcan , Cheng Duan , Kent Wires , Lin Hua
发明人： Jian-Guo Chen , Nevin Heintze , Hakan Pekcan , Cheng Duan , Kent Wires , Lin Hua
IPC分类号： H04L12/28
CPC分类号： H04L69/22
摘要： An apparatus and method are provided for extracting connection information from a traffic header in a communications network. The apparatus includes a first storage element containing a first look-up table for determining a first data packet header offset and data size for extracting a communications protocol type from the header and a second storage element containing a second look-up table for determining from the communications protocol type a second data packet header offset and second data size for extracting a connection address from the header. The storage elements may be in the form of content-addressable memories. Exception handling and hardware initialization can be controlled by a system processor.
摘要翻译： 提供了一种用于从通信网络中的业务报头提取连接信息的装置和方法。 该装置包括第一存储元件，该第一存储元件包含用于确定第一数据包标题偏移的第一查找表和用于从标题中提取通信协议类型的数据大小，以及第二存储元件，其包含第二查找表，用于从 通信协议类型为从头部提取连接地址的第二数据分组报头偏移和第二数据大小。 存储元件可以是可内容寻址的存储器的形式。 异常处理和硬件初始化可由系统处理器控制。
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