CHECKING OUTPUT FROM MULTIPLE EXECUTION UNITS
    1.
    发明申请
    CHECKING OUTPUT FROM MULTIPLE EXECUTION UNITS 有权
    从多个执行单位检查输出

    公开(公告)号:US20080307275A1

    公开(公告)日:2008-12-11

    申请号:US11759832

    申请日:2007-06-07

    IPC分类号: G06F11/277

    CPC分类号: G06F11/27

    摘要: Provided are a method and system checking output from multiple execution units. Execution units concurrently execute test instructions to generate test output, wherein test instructions are transferred to the execution units from a cache coupled to the execution units over a bus. The test output from the execution units is compared to determine whether the output from the execution units indicates the execution units are properly concurrently executing test instructions. The result of the comparing of the test output are forwarded to a design test unit.

    摘要翻译: 提供了从多个执行单元检查输出的方法和系统。 执行单元同时执行测试指令以生成测试输出,其中测试指令通过总线从耦合到执行单元的高速缓存传送到执行单元。 比较来自执行单元的测试输出,以确定执行单元的输出是否指示执行单元正确地同时执行测试指令。 将测试输出进行比较的结果转发给设计测试单元。

    ACTIVATING A DESIGN TEST MODE IN A GRAPHICS CARD HAVING MULTIPLE EXECUTION UNITS
    2.
    发明申请
    ACTIVATING A DESIGN TEST MODE IN A GRAPHICS CARD HAVING MULTIPLE EXECUTION UNITS 有权
    在具有多个执行单位的图形卡中激活设计测试模式

    公开(公告)号:US20080307261A1

    公开(公告)日:2008-12-11

    申请号:US11759840

    申请日:2007-06-07

    IPC分类号: G06F11/27

    CPC分类号: G06F11/27

    摘要: Provided are a method and system for activating a design test mode in a graphics card having multiple execution units. A design test mode is activated in a graphics module comprising multiple execution units coupled to a cache on a bus. The bus is configured to return test instructions from the cache to the execution units in response to a request from one execution unit for the test instructions from the cache in the design test mode. The execution units execute the test instructions during the design test mode. Interrupts are prevented during the design test mode.

    摘要翻译: 提供了一种用于激活具有多个执行单元的图形卡中的设计测试模式的方法和系统。 在包括耦合到总线上的高速缓存的多个执行单元的图形模块中激活设计测试模式。 总线被配置为响应于来自一个执行单元的来自在设计测试模式中的高速缓存的测试指令的请求,将测试指令从高速缓存返回到执行单元。 执行单元在设计测试模式期间执行测试指令。 中断在设计测试模式下被阻止。