公开(公告)号：US20230361223A1

公开(公告)日：2023-11-09

申请号：US17662101

申请日：2022-05-05

Applicant: Allegro MicroSystems, LLC

Inventor： Sagar Saxena ,  Washington Lamar ,  Maxim Klebanov ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

IPC: H01L29/87 ,  H01L29/06

CPC classification number: H01L29/87 ,  H01L29/0684

Abstract: In one aspect, a diode includes a substrate having a first type dopant; a buried layer having a second type dopant and formed within the substrate; an epitaxial layer having the second type dopant and formed above the buried layer; and a plurality of regions having the first type dopant within the epitaxial layer. The plurality of regions includes a first region, a second region, and a third region. The diode also includes a base well having the first type dopant and located within the epitaxial layer and in contact with the third and fourth regions. In a reverse-bias mode, the diode is an electrostatic discharge (ESD) clamp and forms parasitic transistors comprising a first bipolar junction transistor (BJT), a second BJT and a third BJT.

公开(公告)号：US11967650B2

公开(公告)日：2024-04-23

申请号：US17662101

申请日：2022-05-05

Applicant: Allegro MicroSystems, LLC

Inventor： Sagar Saxena ,  Washington Lamar ,  Maxim Klebanov ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

IPC: H01L29/87 ,  H01L29/06

CPC classification number: H01L29/87 ,  H01L29/0684

Abstract: In one aspect, a diode includes a substrate having a first type dopant; a buried layer having a second type dopant and formed within the substrate; an epitaxial layer having the second type dopant and formed above the buried layer; and a plurality of regions having the first type dopant within the epitaxial layer. The plurality of regions includes a first region, a second region, and a third region. The diode also includes a base well having the first type dopant and located within the epitaxial layer and in contact with the third and fourth regions. In a reverse-bias mode, the diode is an electrostatic discharge (ESD) clamp and forms parasitic transistors comprising a first bipolar junction transistor (BJT), a second BJT and a third BJT.

公开(公告)号：US11195826B2

公开(公告)日：2021-12-07

申请号：US16776680

申请日：2020-01-30

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Washington Lamar ,  Sagar Saxena ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

IPC: H01L27/02 ,  H02H9/04 ,  H01L29/866

Abstract: In one aspect an electronic device includes a substrate having one of a p-type doping or an n-type doping, a first well in the substrate, a second well in the substrate, a third well in the substrate between the first and second wells, a first terminal connected to the first well, a second terminal connected to the second well, an electrostatic discharge (ESD) clamp connected to the first and second terminals and a transient voltage source connected to the third well. A doping type of the first, second and third wells is the other one of the p-type or n-type doping. The ESD clamp is configured to clamp the first and second wells at a clamp voltage during an ESD event and the transient voltage source is configured to provide a voltage during the ESD event that is less than the clamp voltage.

公开(公告)号：US20210242193A1

公开(公告)日：2021-08-05

申请号：US16776680

申请日：2020-01-30

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Washington Lamar ,  Sagar Saxena ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

IPC: H01L27/02 ,  H02H9/04 ,  H01L29/866

Abstract: In one aspect an electronic device includes a substrate having one of a p-type doping or an n-type doping, a first well in the substrate, a second well in the substrate, a third well in the substrate between the first and second wells, a first terminal connected to the first well, a second terminal connected to the second well, an electrostatic discharge (ESD) clamp connected to the first and second terminals and a transient voltage source connected to the third well. A doping type of the first, second and third wells is the other one of the p-type or n-type doping. The ESD clamp is configured to clamp the first and second wells at a clamp voltage during an ESD event and the transient voltage source is configured to provide a voltage during the ESD event that is less than the clamp voltage.