公开(公告)号：US09048823B2

公开(公告)日：2015-06-02

申请号：US13930662

申请日：2013-06-28

申请人： Altera Corporation

发明人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

IPC分类号： H03K3/017 ,  H03K5/156 ,  H03K19/094 ,  H03K19/0185

CPC分类号： H03K5/1565 ,  H03K19/018592 ,  H03K19/09429

摘要： Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

摘要翻译： 提供了具有时钟发生和分配电路的集成电路。 集成电路可以包括被配置为生成作为彼此的延迟版本的多个时钟信号的锁相环。 时钟信号可以使用串行连接的时钟缓冲器块分布到集成电路上的各个区域。 每个缓冲块可以包括并联耦合的双向缓冲电路对。 每个缓冲电路可以具有被配置为接收输入时钟信号的第一输入，提供输入时钟信号的校正版本的输出（例如，提供具有期望的占空比的输出时钟信号的输出）， 第二输入端，接收用于设定所述输出时钟信号的期望占空比的第一延迟时钟信号;以及第三输入端，其接收至少当所述第一延迟时钟信号上升时为高的第二延迟时钟信号。

公开(公告)号：US20130285725A1

公开(公告)日：2013-10-31

申请号：US13930662

申请日：2013-06-28

申请人： Altera Corporation

发明人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

IPC分类号： H03K5/156

CPC分类号： H03K5/1565 ,  H03K19/018592 ,  H03K19/09429

摘要： Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.