Cache memory error analysis and management thereof

    公开(公告)号:US11868204B1

    公开(公告)日:2024-01-09

    申请号:US17548270

    申请日:2021-12-10

    CPC classification number: G06F11/079 G06F11/073 G06F11/0751

    Abstract: A system includes an obsolete cache-line vector having a plurality of memory elements, wherein each memory element has a one-to-one correspondence to a cache line entry of a cache memory. The vector can capture cache line errors that occur at different times from an error detection logic associated with the cache memory. A counter can be coupled to the obsolete cache-line vector for tracking how many of the memory elements in the vector are activated. When a predetermined threshold is reached, a threshold comparator can release a trigger for further analysis. An error events logger can be used to track all of the errors that occurred. The error events logger can also use a time stamp, which can assist the RAS system in analyzing a correlation between the errors, such as patterns that occur and time differences between the errors.

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