公开(公告)号：US20240039652A1

公开(公告)日：2024-02-01

申请号：US18021363

申请日：2021-07-21

Applicant: Analog Devices, Inc.

Inventor： Hakim SAHEB

IPC: H04J3/06 ,  H04L49/90

CPC classification number: H04J3/0685 ,  H04L49/90

Abstract: A digital front end processor is proposed that includes a transmit channel and/or a receive channel. The digital front end processor may be a part of a multi-antenna wireless communication system or any other system including multiple data channels for which data output is to be in synchronization. The digital front end processor includes a data buffer to receive input data in synchronization with a first strobe signal and generate output data based in the input data. The digital front end processor is to synchronize the output data of transmit channels or receive channels of a plurality of digital front end processors based on a data delay applied to the input data.

公开(公告)号：US20230308131A1

公开(公告)日：2023-09-28

申请号：US18022735

申请日：2021-07-21

Applicant: Analog Devices, Inc.

Inventor： Hakim SAHEB

IPC: H04B1/7136

CPC classification number: H04B1/7136 ,  H04B2201/71384 ,  H04B2001/71365 ,  H04B2201/71353

Abstract: Multiple transmit and receive channels in a communication transceiver may be dynamically configured using corresponding channel registers. In order to support fast frequency hopping, arbitrary sample rate change or profile switching, the present disclosure proposes a profile-based direct memory access (PDMA) that can be used to transfer data from a memory and program specific profile registers in a randomly accessed addressing manner. PDMAs can offload the system processor from reprogramming many system registers based on external or internal events in a multi channels communication system. Furthermore, a PDMA based DMA controller is proposed to configure the fast frequency hopping registers of the transceiver based on PDMA.