公开(公告)号：US20160034399A1

公开(公告)日：2016-02-04

申请号：US14450145

申请日：2014-08-01

Applicant: Analog Devices Technology

Inventor： Abhijit Giri ,  Saurbh Srivastava ,  Michael S. Allen

IPC: G06F12/08

CPC classification number: G06F12/0848 ,  G06F2212/1024

Abstract: Digital signal processors often operate on two operands per instruction, and it is desirable to retrieve both operands in one cycle. Some data caches connect to the processor over two busses and internally uses two or more memory banks to store cache lines. The allocation of cache lines to specific banks is based on the address that the cache line is associated. When two memory accesses map to the same memory bank, fetching the operands incurs extra latency because the accesses are serialized. An improved bank organization for providing conflict-free dual-data cache access—a bus-based data cache system having two data buses and two memory banks—is disclosed. Each memory bank works as a default memory bank for the corresponding data bus. As long as the two values of data being accessed belong to two separate data sets assigned to the two respective data buses, memory bank conflicts are avoided.

Abstract translation: 数字信号处理器通常在每个指令的两个操作数上操作，并且期望在一个周期内检索两个操作数。 一些数据高速缓存通过两个总线连接到处理器，并且内部使用两个或多个存储体来存储高速缓存行。 将高速缓存行分配给特定存储区基于高速缓存行关联的地址。 当两个内存访问映射到同一个存储区时，获取操作数会导致额外的延迟，因为访问是序列化的。 公开了一种用于提供无冲突双数据高速缓存访​​问的改进的银行组织 - 具有两个数据总线和两个存储体的基于总线的数据高速缓存系统。 每个存储体都作为相应数据总线的默认存储体。 只要访问的数据的两个值属于分配给两个相应的数据总线的两个单独的数据集，就避免了存储体冲突。