摘要:
Low density parity check (LDPC) codes (LDPCCs) have an identical code blocklength and different code rates. At least one of the rows of a higher-rate LDPC matrix is obtained by combining a plurality of rows of a lower-rate LDPC matrix with the identical code blocklength as the higher-rate LDPC matrix.
摘要:
Low density parity check (LDPC) decoders are described utilizing a sequential schedule called Zigzag LBP (Z-LBP), for a layered belief propagation (LBP) architecture. Z-LBP has a lower computational complexity per iteration than variable-node-centric LBP (V-LBP), while being simpler than flooding and check-node-centric LBP (C-LBP). For QC-LDPC codes where the sub-matrices can have at most one “1” per column and one “1” per row, Z-LBP can perform partially-parallel decoding with the same performance as C-LBP. The decoder comprises a control circuit and memory coupled to a parity check matrix. Message passage is performed within Z-LBP in a first direction on odd iterations, and in a second direction on even iterations. As a result, a smaller parity check matrix can be utilized, while convergence can be more readily attained. The inventive method and apparatus can also be implemented for partially-parallel architectures.
摘要:
Low density parity check (LDPC) decoders are described utilizing a sequential schedule called Zigzag LBP (Z-LBP), for a layered belief propagation (LBP) architecture. Z-LBP has a lower computational complexity per iteration than variable-node-centric LBP (V-LBP), while being simpler than flooding and check-node-centric LBP (C-LBP). For QC-LDPC codes where the sub-matrices can have at most one “1” per column and one “1” per row, Z-LBP can perform partially-parallel decoding with the same performance as C-LBP. The decoder comprises a control circuit and memory coupled to a parity check matrix. Message passage is performed within Z-LBP in a first direction on odd iterations, and in a second direction on even iterations. As a result, a smaller parity check matrix can be utilized, while convergence can be more readily attained. The inventive method and apparatus can also be implemented for partially-parallel architectures.