公开(公告)号：US11023162B2

公开(公告)日：2021-06-01

申请号：US16548784

申请日：2019-08-22

Applicant: Apple Inc.

Inventor： Jeffrey T. Brady ,  Sindhuja Sethuraman ,  Frank W. Liljeros ,  Adil M. Sadik

IPC: G06F12/0871 ,  G06F3/06

Abstract: Techniques are disclosed relating to caches that support transient storage fields for cache entries. In some embodiments, cache circuitry includes a set of multiple cache entries that each include a tag field and a data field. In some embodiments, transient storage circuitry includes a transient storage field for each of the multiple cache entries. In some embodiments, cache control circuitry stores received first data in the data field of a cache entry and stores received transient data in a corresponding transient storage field. In response to an eviction determination for the cache entry, however, the cache control circuitry may write the first data but not the transient data to a backing memory for the cache circuitry. In various embodiments, disclosed techniques may allow caching additional data that is transient without increasing bandwidth to the backing memory.

公开(公告)号：US20210055883A1

公开(公告)日：2021-02-25

申请号：US16548784

申请日：2019-08-22

Applicant: Apple Inc.

Inventor： Jeffrey T. Brady ,  Sindhuja Sethuraman ,  Frank W. Liljeros ,  Adil M. Sadik

IPC: G06F3/06 ,  G06F12/0871

Abstract: Techniques are disclosed relating to caches that support transient storage fields for cache entries. In some embodiments, cache circuitry includes a set of multiple cache entries that each include a tag field and a data field. In some embodiments, transient storage circuitry includes a transient storage field for each of the multiple cache entries. In some embodiments, cache control circuitry stores received first data in the data field of a cache entry and stores received transient data in a corresponding transient storage field. In response to an eviction determination for the cache entry, however, the cache control circuitry may write the first data but not the transient data to a backing memory for the cache circuitry. In various embodiments, disclosed techniques may allow caching additional data that is transient without increasing bandwidth to the backing memory.