公开(公告)号：US20180276128A1

公开(公告)日：2018-09-27

申请号：US15996776

申请日：2018-06-04

Applicant: Apple Inc.

Inventor： Bikram Saha ,  Harshavardhan Kaushikkar ,  Sukalpa Biswas ,  Prashant Jain

IPC: G06F12/0842

CPC classification number: G06F12/0842 ,  G06F2212/1024 ,  G06F2212/283

Abstract: In an embodiment, an apparatus includes multiple memory resources, and a resource table that includes entries that correspond to respective memory resources of the multiple memory resources. The apparatus also includes a circuit configured to receive a first memory command. The first memory command is associated with a subset of the multiple memory resources. For each memory resource of the subset, the circuit is also configured to set a respective indicator associated with the first memory command, and to store a first value in a first entry of the resource table in response to a determination that the respective memory resource is unavailable. The circuit is also configured to store a second value in each entry of the resource table that corresponds to a memory resource of the subset in response to a determination that an entry corresponding to a given memory resource of the subset includes the first value.

公开(公告)号：US20170242798A1

公开(公告)日：2017-08-24

申请号：US15052000

申请日：2016-02-24

Applicant: Apple Inc.

Inventor： Bikram Saha ,  Harshavardhan Kaushikkar ,  Sukalpa Biswas ,  Prashant Jain

IPC: G06F12/08

CPC classification number: G06F12/0842 ,  G06F2212/1024 ,  G06F2212/283

Abstract: In an embodiment, an apparatus includes multiple memory resources, and a resource table that includes entries that correspond to respective memory resources of the multiple memory resources. The apparatus also includes a circuit configured to receive a first memory command. The first memory command is associated with a subset of the multiple memory resources. For each memory resource of the subset, the circuit is also configured to set a respective indicator associated with the first memory command, and to store a first value in a first entry of the resource table in response to a determination that the respective memory resource is unavailable. The circuit is also configured to store a second value in each entry of the resource table that corresponds to a memory resource of the subset in response to a determination that an entry corresponding to a given memory resource of the subset includes the first value.

公开(公告)号：US10169235B2

公开(公告)日：2019-01-01

申请号：US14969360

申请日：2015-12-15

Applicant: Apple Inc.

Inventor： Bikram Saha ,  Harshavardhan Kaushikkar ,  Wolfgang H. Klingauf

IPC: G06F12/084 ,  G06F12/0815

Abstract: In an embodiment, an apparatus includes control circuitry and a memory configured to store a plurality of access instructions. The control circuitry is configured to determine an availability of a resource associated with a given access instruction of the plurality of access instructions. The associated resource is included in a plurality of resources. The control circuitry is also configured to determine a priority level of the given access instruction in response to a determination that the associated resource is unavailable. The control circuit is further configured to add the given access instruction to a subset of the plurality of access instructions in response to a determination that the priority level is greater than a respective priority level of each access instruction in the subset. The control circuit is also configured to remove the given access instruction from the subset in response to a determination that the associated resource is available.

公开(公告)号：US09990294B2

公开(公告)日：2018-06-05

申请号：US15052000

申请日：2016-02-24

Applicant: Apple Inc.

Inventor： Bikram Saha ,  Harshavardhan Kaushikkar ,  Sukalpa Biswas ,  Prashant Jain

IPC: G06F12/08 ,  G06F12/0842

CPC classification number: G06F12/0842 ,  G06F2212/1024 ,  G06F2212/283

Abstract: In an embodiment, an apparatus includes multiple memory resources, and a resource table that includes entries that correspond to respective memory resources of the multiple memory resources. The apparatus also includes a circuit configured to receive a first memory command. The first memory command is associated with a subset of the multiple memory resources. For each memory resource of the subset, the circuit is also configured to set a respective indicator associated with the first memory command, and to store a first value in a first entry of the resource table in response to a determination that the respective memory resource is unavailable. The circuit is also configured to store a second value in each entry of the resource table that corresponds to a memory resource of the subset in response to a determination that an entry corresponding to a given memory resource of the subset includes the first value.

公开(公告)号：US20170168940A1

公开(公告)日：2017-06-15

申请号：US14969360

申请日：2015-12-15

Applicant: Apple Inc.

Inventor： Bikram Saha ,  Harshavardhan Kaushikkar ,  Wolfgang H. Klingauf

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/084 ,  G06F2212/621

Abstract: In an embodiment, an apparatus includes control circuitry and a memory configured to store a plurality of access instructions. The control circuitry is configured to determine an availability of a resource associated with a given access instruction of the plurality of access instructions. The associated resource is included in a plurality of resources. The control circuitry is also configured to determine a priority level of the given access instruction in response to a determination that the associated resource is unavailable. The control circuit is further configured to add the given access instruction to a subset of the plurality of access instructions in response to a determination that the priority level is greater than a respective priority level of each access instruction in the subset. The control circuit is also configured to remove the given access instruction from the subset in response to a determination that the associated resource is available.