公开(公告)号：US10713109B2

公开(公告)日：2020-07-14

申请号：US15859189

申请日：2017-12-29

Applicant: Apple Inc.

Inventor： Anthony J. Tarlano ,  Nikhil A. Desai ,  Chandrasekaran Jagadeesan ,  Subash Sundaresan

IPC: G06F11/00 ,  G06F11/07 ,  G06F9/38 ,  G06N5/02 ,  G06F9/54 ,  G06N20/00

Abstract: Embodiments described herein provide a predictive failure analysis that enables design-time error and exception handling techniques to be supplemented or assisted by a predictive failure analysis system. One embodiment provides an electronic device, comprising a non-transitory machine-readable medium to store instructions; one or more processors to execute the instructions; and a memory coupled to the one or more processors, the memory to store the instructions which, when executed by the one or more processors, cause the one or more processors to receive injection of dynamic error detection logic into the instructions, the dynamic error handling logic including an error handling update to indicate a response to a predicted failure; receive a set of events indicative of the predicted failure; and respond to the set of events according to the error handling update.

公开(公告)号：US20190102244A1

公开(公告)日：2019-04-04

申请号：US15859189

申请日：2017-12-29

Applicant: Apple Inc.

Inventor： Anthony J. Tarlano ,  Nikhil A. Desai ,  Chandrasekaran Jagadeesan ,  Subash Sundaresan

IPC: G06F11/07 ,  G06F9/38 ,  G06F9/54 ,  G06N5/02

Abstract: Embodiments described herein provide a predictive failure analysis that enables design-time error and exception handling techniques to be supplemented or assisted by a predictive failure analysis system. One embodiment provides an electronic device, comprising a non-transitory machine-readable medium to store instructions; one or more processors to execute the instructions; and a memory coupled to the one or more processors, the memory to store the instructions which, when executed by the one or more processors, cause the one or more processors to receive injection of dynamic error detection logic into the instructions, the dynamic error handling logic including an error handling update to indicate a response to a predicted failure; receive a set of events indicative of the predicted failure; and respond to the set of events according to the error handling update.