Circuit For Combined Down Sampling And Correction Of Image Data

    公开(公告)号:US20240029198A1

    公开(公告)日:2024-01-25

    申请号:US18230560

    申请日:2023-08-04

    Applicant: Apple Inc.

    CPC classification number: G06T3/4007 H04N23/88

    Abstract: A foveated down sampling and correction (FDS-C) circuit for combined down sampling and correction of chromatic aberrations in images. The FDS-C circuit performs down sampling and interpolation of pixel values of a first subset of pixels of a color in a raw image using down sampling scale factors and first interpolation coefficients to generate first corrected pixel values for pixels of the color in a first corrected version of the raw image. The FDS-C circuit further performs interpolation of pixel values of a second subset of the pixels in the first corrected version using second interpolation coefficients to generate second corrected pixel values for pixels of the color in a second corrected version of the raw image. Pixels in the first subset are arranged in a first direction, pixels in the second subset are arranged in a second direction, and the down sampling scale factors vary along the first direction.

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