SIMULTANEOUS DATA TRANSFER AND ERROR CONTROL TO REDUCE LATENCY AND IMPROVE THROUGHPUT TO A HOST
    1.
    发明申请
    SIMULTANEOUS DATA TRANSFER AND ERROR CONTROL TO REDUCE LATENCY AND IMPROVE THROUGHPUT TO A HOST 审中-公开
    同时进行数据传输和错误控制以减少延迟并改善对主机的影响

    公开(公告)号:US20140195872A1

    公开(公告)日:2014-07-10

    申请号:US14150667

    申请日:2014-01-08

    Applicant: Apple Inc.

    CPC classification number: H04L1/08 G06F11/10 H04L1/004

    Abstract: The disclosed embodiments provide a system that transfers data from a storage device to a host. The system includes a communication mechanism that receives a request to read a set of blocks from the host. Next, upon reading each block from the set of blocks from the storage device, the communication mechanism transfers the block over an interface with the host. The system also includes an error-detection apparatus that performs error detection on the block upon reading the block, and an error-correction apparatus that performs error correction on the block if an error is detected in the block. The communication mechanism may then retransfer the block to the host after the error is removed from the block.

    Abstract translation: 所公开的实施例提供了将数据从存储设备传送到主机的系统。 该系统包括一个通信机制,其接收从主机读取一组块的请求。 接下来,在从存储装置读取块集合中的每个块时,通信机制通过与主机的接口传送块。 该系统还包括在读取该块时对块执行错误检测的错误检测装置,以及如果在该块中检测到错误则对该块执行错误校正的纠错装置。 然后,在从块中移除错误之后,通信机制可以将块重新传送到主机。

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