Scan Data Transfer Circuits for Multi-die Chip Testing

    公开(公告)号:US20250093416A1

    公开(公告)日:2025-03-20

    申请号:US18391145

    申请日:2023-12-20

    Applicant: Apple Inc.

    Abstract: An apparatus includes a first set of scan-enabled flip-flop circuits may be configured to shift a scan-chain pattern from a first test input node to a first test output node using a first clock signal. A particular lockup latch may be coupled to the first test output node and to a second test input node. This particular lockup latch may be configured to, when enabled, delay propagation of the scan-chain pattern from the first test output node to the second test input node. A second set of scan-enabled flip-flop circuits may be configured to shift the scan-chain pattern from the second test input node to a second test output node using a second clock signal, different from the first clock signal. A control circuit may be configured to determine whether to enable the particular lockup latch using a particular scan test signal.

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