公开(公告)号：US12009760B2

公开(公告)日：2024-06-11

申请号：US18341474

申请日：2023-06-26

Applicant: Apple Inc.

Inventor： Sujeet Milind Patole ,  Cheung-Wei Lam ,  Mahmoud N Mahmoud

IPC: H02M7/48 ,  H02M1/00 ,  H02M1/12 ,  H02M7/529

CPC classification number: H02M7/4803 ,  H02M1/0041 ,  H02M1/12 ,  H02M7/529

Abstract: An electronic device may include an inverter. The inverter may convert direct current (DC) power to alternating current (AC) power. The inverter may use a clock signal at a given frequency to output corresponding alternating current signals at the given frequency. The inverter may receive a dithered clock signal that is frequency dithered using a modulating signal. The dithered clock signal may have at least three different frequency levels during a repeated cycle of the modulating signal. The at least three different frequency levels may include a fundamental frequency, a first frequency that is lower than the fundamental frequency, and a second frequency that is higher than the fundamental frequency. The dithered clock signal may be, during the repeated cycle of the modulating signal, at the fundamental frequency for fewer total periods than at the first frequency and for fewer total periods than at the second frequency.

公开(公告)号：US11736032B1

公开(公告)日：2023-08-22

申请号：US18164291

申请日：2023-02-03

Applicant: Apple Inc.

Inventor： Sujeet Milind Patole ,  Cheung-Wei Lam ,  Mahmoud N Mahmoud

IPC: H02M7/48 ,  H02M1/12 ,  H02M7/529 ,  H02M1/00

CPC classification number: H02M7/4803 ,  H02M1/0041 ,  H02M1/12 ,  H02M7/529

Abstract: An electronic device may include an inverter. The inverter may convert direct current (DC) power to alternating current (AC) power. The inverter may use a clock signal at a given frequency to output corresponding alternating current signals at the given frequency. The inverter may receive a dithered clock signal that is frequency dithered using a modulating signal. The dithered clock signal may have at least three different frequency levels during a repeated cycle of the modulating signal. The at least three different frequency levels may include a fundamental frequency, a first frequency that is lower than the fundamental frequency, and a second frequency that is higher than the fundamental frequency. The dithered clock signal may be, during the repeated cycle of the modulating signal, at the fundamental frequency for fewer total periods than at the first frequency and for fewer total periods than at the second frequency.