公开(公告)号：US10970077B2

公开(公告)日：2021-04-06

申请号：US16437739

申请日：2019-06-11

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Mridul Agarawal ,  Nikhil Gupta

IPC: G06F9/38

Abstract: In an embodiment, a processor includes a load/store unit that executes load/store operations. The load/store unit may implement a two-level load queue. One of the load queues, referred to as a load retirement queue (LRQ), may track load operations from initial execution to retirement. Ordering constraints may be enforced using the LRQ. The other load queue, referred to as a load execution queue (LEQ), may track loads from initial execution to forwarding of data. Replay may be managed by the LEQ. In an embodiment, the LEQ may be smaller than the LRQ, which may permit the management of replay while still meeting timing requirements. Additionally, the larger LRQ may permit more load operations to be pending (not retired) in the processor, widening the window for out of order execution and supporting potentially higher processor performance.