公开(公告)号：US20250169117A1

公开(公告)日：2025-05-22

申请号：US19029421

申请日：2025-01-17

Applicant: Applied Materials, Inc.

Inventor： Yun-Chu Tsai ,  Dejiu Fan ,  Jung Bae Kim ,  Yang Ho Bae ,  Rodney Shunleong Lim ,  Dong Kil Yim

IPC: H10D30/67 ,  H10D30/01

Abstract: A transistor device includes a channel region, a first source/drain region adjacent to a first end of the channel region and a second source/drain region adjacent to a second end of the channel region, a gate structure disposed on the channel region, the first source/drain region and the second source/drain region, and an interlayer dielectric (ILD) structure disposed on the gate structure. The ILD structure includes a first dielectric layer including a first set of sublayers. The first set of sublayers includes a first sublayer including a first dielectric material having a first hydrogen concentration and a second sublayer including the first dielectric material having a second hydrogen concentration lower than the first hydrogen concentration. The ILD structure further includes a second dielectric layer including a second set of sublayers. The second set of sublayers includes a third sublayer including a second dielectric material different from the first dielectric material.

公开(公告)号：US20250169116A1

公开(公告)日：2025-05-22

申请号：US19029403

申请日：2025-01-17

Applicant: Applied Materials, Inc.

Inventor： Yun-Chu Tsai ,  Dejiu Fan ,  Jung Bae Kim ,  Yang Ho Bae ,  Rodney Shunleong Lim ,  Dong Kil Yim

IPC: H10D30/67 ,  H10D30/01

Abstract: A method includes forming a first dielectric layer of an interlayer dielectric (ILD) structure of a transistor device, wherein forming the first dielectric layer includes forming a first sublayer including a first dielectric material on a gate structure and forming a second sublayer including the first dielectric material on the first sublayer, wherein forming the first sublayer includes depositing the first dielectric material of the first sublayer at a first deposition rate, and wherein forming the second sublayer includes depositing the first dielectric material of the second sublayer at a second deposition rate less than the first deposition rate, and forming a second dielectric layer of the ILD structure by forming a third sublayer including a second dielectric material on the first dielectric layer using a third deposition rate, wherein the second dielectric material is different from the first dielectric material.

公开(公告)号：US20230290883A1

公开(公告)日：2023-09-14

申请号：US17691548

申请日：2022-03-10

Applicant: Applied Materials, Inc.

Inventor： Yun-Chu Tsai ,  Dejiu Fan ,  Jung Bae Kim ,  Yang Ho Bae ,  Rodney Shunleong Lim ,  Dong Kil Yim

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78672 ,  H01L29/66742

Abstract: A transistor device includes a channel region, a first source/drain region adjacent to a first end of the channel region and a second source/drain region adjacent to a second end of the channel region, a gate structure disposed on the channel region, the first source/drain region and the second source/drain region, and an interlayer dielectric (ILD) structure disposed on the gate structure. The ILD structure includes a first dielectric layer including a first set of sublayers. The first set of sublayers includes a first sublayer including a first dielectric material having a first hydrogen concentration and a second sublayer including the first dielectric material having a second hydrogen concentration lower than the first hydrogen concentration. The ILD structure further includes a second dielectric layer including a second set of sublayers. The second set of sublayers includes a third sublayer including a second dielectric material different from the first dielectric material.

公开(公告)号：US12261226B2

公开(公告)日：2025-03-25

申请号：US17691548

申请日：2022-03-10

Applicant: Applied Materials, Inc.

Inventor： Yun-Chu Tsai ,  Dejiu Fan ,  Jung Bae Kim ,  Yang Ho Bae ,  Rodney Shunleong Lim ,  Dong Kil Yim

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/786

Abstract: A transistor device includes a channel region, a first source/drain region adjacent to a first end of the channel region and a second source/drain region adjacent to a second end of the channel region, a gate structure disposed on the channel region, the first source/drain region and the second source/drain region, and an interlayer dielectric (ILD) structure disposed on the gate structure. The ILD structure includes a first dielectric layer including a first set of sublayers. The first set of sublayers includes a first sublayer including a first dielectric material having a first hydrogen concentration and a second sublayer including the first dielectric material having a second hydrogen concentration lower than the first hydrogen concentration. The ILD structure further includes a second dielectric layer including a second set of sublayers. The second set of sublayers includes a third sublayer including a second dielectric material different from the first dielectric material.