公开(公告)号：US20150150009A1

公开(公告)日：2015-05-28

申请号：US14090610

申请日：2013-11-26

Applicant: Applied Micro Circuits Corporation

Inventor： Dimitri MAVROIDIS

IPC: G06F9/48 ,  G06F9/52

CPC classification number: H04L47/10

Abstract: Systems and methods for multi-channel signal processing by virtue of packet-based time-slicing with single processing core logic. The processing core logic is configured to receive data streams from the multiple communication channels at a data processing unit, and process data fragments of the data streams in a time-sliced manner. The processing core logic can switch from processing a first data fragment of a first data stream to processing a first data fragment of a second data stream at an end of a time slice, wherein the time slice is determined by a fragment boundary associated with the data fragment of the first data stream.

Abstract translation: 凭借采用单处理核心逻辑的基于分组的时间分片，多信道信号处理的系统和方法。 处理核心逻辑被配置为在数据处理单元处从多个通信信道接收数据流，并且以时间分割方式处理数据流的数据片段。 处理核心逻辑可以从处理第一数据流的第一数据片段切换到在时间片段的末尾处理第二数据流的第一数据片段，其中所述时间片由与所述数据相关联的片段边界确定 第一个数据流的片段。

公开(公告)号：US20150163024A1

公开(公告)日：2015-06-11

申请号：US14099554

申请日：2013-12-06

Applicant: Applied Micro Circuits Corporation

Inventor： Dimitri MAVROIDIS

IPC: H04L5/00

CPC classification number: H04L47/10

Abstract: Systems and methods for multi-channel signal processing by a series of single processing core logic circuitries in time-slicing. A first logic circuitry is configured to process multiple data streams from multiple channels in a first cycle-based time-sliced schedule. A time slice in the first cycle-based time-sliced schedule comprises a predetermined number of clock cycles allocated to a corresponding data stream. A second logic circuitry is coupled to the first logic circuitry and configured to process the data streams in a first fragment-based time-sliced schedule. A time slice in the first fragment-based time-sliced schedule is determined based on a predetermined boundary associated with the data fragment and is allocated to process a data fragment of the data streams.

Abstract translation: 通过一系列单处理核心逻辑电路在时间分片中进行多通道信号处理的系统和方法。 第一逻辑电路被配置为在基于第一周期的时间分片调度中处理来自多个信道的多个数据流。 基于第一周期的时间分片表中的时间片包括分配给相应数据流的预定数量的时钟周期。 第二逻辑电路被耦合到第一逻辑电路并且被配置为以基于片段的第一片段时间片表进行数据流的处理。 基于与数据片段相关联的预定边界来确定基于片段的第一片段时间片段中的时间片，并且被分配以处理数据流的数据片段。