公开(公告)号：US11914518B1

公开(公告)日：2024-02-27

申请号：US17949607

申请日：2022-09-21

Applicant: Arm Limited

Inventor： Yoav Asher Levy ,  Elad Kadosh ,  Jakob Axel Fries ,  Lior-Levi Bandal

IPC: G06F12/0884

CPC classification number: G06F12/0884 ,  G06F2212/1021

Abstract: A cache is provided having a plurality of entries for storing data. In response to a given access request, lookup circuitry performs a lookup operation in the cache to determine whether one of the entries in the cache is allocated to store data associated with the memory address indicated by the given access request, with a hit indication or a miss indication being generated dependent on the outcome of that lookup operation. During a single lookup period, the lookup circuitry is configured to perform lookup operations in parallel for up to N access requests. In addition, allocation circuitry is provided that is able to determine, during the single lookup period, at least N candidate entries for allocation from amongst the plurality of entries, and to cause one of the candidate entries to be allocated for each of the up to N access requests for which the lookup circuitry generates a miss indication.