公开(公告)号：US20210124694A1

公开(公告)日：2021-04-29

申请号：US16666878

申请日：2019-10-29

Applicant: Arm Limited

Inventor： Fabrice Jean VERPLANKEN

IPC: G06F12/126 ,  G06F12/0846

Abstract: An apparatus and method are described, the apparatus comprising: a cache comprising a plurality of entries, each associated with a partition identifier; storage circuitry to store counters, each indicative of a number of entries in the cache associated with respective partition identifiers; and cache control circuitry responsive to a request identifying a given partition identifier to control allocation of an entry dependent on the counter associated with the given partition identifier. The cache control circuitry increments the counter associated with the given partition identifier in response to an entry associated with the given partition identifier being allocated, and decrements the counter associated with the given partition identifier in response to an entry associated with the given partition identifier being evicted or replaced. When a request to increment the counters is pending, the cache control circuitry prioritises the pending increment request in preference over a request to decrement the counters.

公开(公告)号：US20250110874A1

公开(公告)日：2025-04-03

申请号：US18476659

申请日：2023-09-28

Applicant: Arm Limited

Inventor： Fabrice Jean VERPLANKEN ,  Rakesh RAMAN ,  Nikita PrakashChandra BHANDARI

IPC: G06F12/0808 ,  G06F12/02 ,  G06F13/18

Abstract: Cache invalidation circuitry responds to a cache invalidation command specifying invalidation scope information indicative of at least one invalidation condition, to control a cache to perform an invalidation process to invalidate cache entries satisfying the invalidation condition(s). Cache lookup circuitry issues to the cache a cache lookup request specifying address information, to request that the cache returns a cache lookup response. Cache lookup response filtering circuitry is responsive to a given hit-indicating cache lookup response which provides cached information and invalidation qualifying information returned from a corresponding valid cache entry, to determine whether the given hit-indicating cache lookup response conflicts with an in-progress cache invalidation command, based on the invalidation scope information specified by the in-progress cache invalidation command and the invalidation qualifying information, and when conflict is detected, causes the given hit-indicating cache lookup response to be treated as a miss-indicating cache lookup response.

公开(公告)号：US20170024263A1

公开(公告)日：2017-01-26

申请号：US14807062

申请日：2015-07-23

Applicant: ARM LIMITED

Inventor： Fabrice Jean VERPLANKEN

IPC: G06F9/54

CPC classification number: G06F9/542 ,  G06F9/546

Abstract: Queue storage queues event entries from a hardware event detector that are to be communicated to a software event handler. An event register stores a most recently received event entry. A comparator compares a newly received event entry with the content of the event register and if a match occurs, then these event entries are merged by setting a merged entry bit and discarding the newly received event entry. When a non-matching event entry is received, then the unqueued event within the event register is stored into the queue storage. If the queue storage is empty, then the event register and the comparator are bypassed. When the queue storage becomes empty, then any currently unqueued event within the event register is stored into the queue storage. The event entries may be translation error event entries in a system which translates between virtual addresses and physical addresses.

Abstract translation: 来自硬件事件检测器的队列存储队列事件条目将被传递给软件事件处理程序。 事件寄存器存储最近收到的事件条目。 比较器将新接收的事件条目与事件寄存器的内容进行比较，并且如果发生匹配，则通过设置合并的条目位并丢弃新接收到的事件条目来合并这些事件条目。 当接收到不匹配的事件条目时，事件寄存器内的未排队事件被存储到队列存储器中。 如果队列存储空闲，则旁路事件寄存器和比较器。 当队列存储变为空时，事件寄存器中的任何当前未排队的事件都将存储到队列存储器中。 事件条目可以是在虚拟地址和物理地址之间转换的系统中的转换错误事件条目。