公开(公告)号：US11455268B2

公开(公告)日：2022-09-27

申请号：US16790112

申请日：2020-02-13

Applicant: Arm Limited

Inventor： Matteo Maria Andreozzi ,  Michael Andrew Campbell ,  Giovanni Stea ,  Raffaele Zippo

IPC: G06F13/40 ,  G06F9/48

Abstract: The present disclosure relates generally to electronic interconnects including one or more switches and, more particularly, to delay bound determination for electronic interconnects.

公开(公告)号：US20210255981A1

公开(公告)日：2021-08-19

申请号：US16790112

申请日：2020-02-13

Applicant: Arm Limited

Inventor： Matteo Maria Andreozzi ,  Michael Andrew Campbell ,  Giovanni Stea ,  Raffaele Zippo

IPC: G06F13/40 ,  G06F9/48

Abstract: The present disclosure relates generally to electronic interconnects including one or more switches and, more particularly, to delay bound determination for electronic interconnects.

公开(公告)号：US12153805B2

公开(公告)日：2024-11-26

申请号：US17755507

申请日：2020-09-01

Applicant: ARM LIMITED

Inventor： Michael Andrew Campbell ,  Matteo Maria Andreozzi ,  Lorenzo Biagini ,  Giovanni Stea ,  Ankit Mehta

IPC: G06F3/06

Abstract: Examples of the present disclosure relate to an apparatus comprising interface circuitry to receive memory access commands directed to a memory device, each memory access command specifying a memory address to be accessed. The apparatus comprises scheduler circuitry to store a representation of a plurality of states accessible to the memory device and, based on the representation, determine an order for the received memory access commands. The apparatus comprises dispatch circuitry to receive the received memory access commands from the scheduler circuitry and issue the received memory access commands, in the determined order, to be performed by the memory device.