公开(公告)号：US20210124587A1

公开(公告)日：2021-04-29

申请号：US16662418

申请日：2019-10-24

Applicant: Arm Limited

Inventor： Alexander Alfred HORNUNG ,  Jose GONZALEZ-GONZALEZ

IPC: G06F9/38 ,  G06F9/30

Abstract: Aspects of the present disclosure relate to an apparatus comprising decode circuitry to receive an instruction and identify the received instruction as a load instruction, and prediction circuitry to predict, based on a prediction scheme, a target address of the load instruction, and trigger a speculative memory access in respect of the predicted target address.

公开(公告)号：US20190340124A1

公开(公告)日：2019-11-07

申请号：US16305165

申请日：2017-04-27

Applicant: ARM LIMITED

Inventor： Adnan KHAN ,  Alex James WAUGH ,  Jose GONZALEZ-GONZALEZ

IPC: G06F12/084 ,  G06F12/0817 ,  G06F12/0831

Abstract: An apparatus (300) for processing data comprises a plurality of memory access request sources (102,104) which generate memory access requests. Each of the memory access request sources has a local memory (106,108), and the apparatus also includes a shared memory (110). When the memory access requests are atomic memory access requests, contention may arise over common data. When this occurs, the present technique triggers a switch of processing data in the local memory of a memory access request source to processing data in the shared memory.

公开(公告)号：US20210157730A1

公开(公告)日：2021-05-27

申请号：US16690506

申请日：2019-11-21

Applicant: Arm Limited

Inventor： Alexander Alfred HORNUNG ,  Jose GONZALEZ-GONZALEZ ,  Gregory Andrew CHADWICK

IPC: G06F12/0862

Abstract: An apparatus comprises processing circuitry to issue demand memory access requests to access data stored in a memory system. Stride pattern detection circuitry detects whether a sequence of demand target addresses specified by the demand memory access requests includes two or more constant stride sequences of addresses interleaved within the sequence of demand target addresses. Each constant stride sequence comprises addresses separated by intervals of a constant stride value. Prefetch control circuitry controls issuing of prefetch load requests to prefetch data from the memory system. The prefetch load requests specify prefetch target addresses predicted based on the constant stride sequences detected by the stride pattern detection circuitry.

公开(公告)号：US20190303160A1

公开(公告)日：2019-10-03

申请号：US15939722

申请日：2018-03-29

Applicant: Arm Limited

Inventor： Peter Richard GREENHALGH ,  Frederic Claude Marie PIRY ,  Jose GONZALEZ-GONZALEZ

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus and method of operating an apparatus are provided. The apparatus comprises execution circuitry to perform data processing operations specified by instructions and instruction retrieval circuitry to retrieve the instructions from memory, wherein the instructions comprise branch instructions. The instruction retrieval circuitry comprises branch target storage to store target instruction addresses for the branch instructions and branch target prefetch circuitry to prepopulate the branch target storage with predicted target instruction addresses for the branch instructions. An improved hit rate in the branch target storage may thereby be supported.