公开(公告)号：US10901865B2

公开(公告)日：2021-01-26

申请号：US16374103

申请日：2019-04-03

Applicant: Arm Limited

Inventor： Richard F Bryant ,  Sridharan Balasubramanian ,  Joseph Anthony Delgross

IPC: G06F11/20 ,  G06F11/16

Abstract: An apparatus has two or more processing elements to redundantly process a same processing workload; and divergence detection circuitry to detect divergence between the plurality of processing elements. When a correctable error is detected by error detection circuitry of an erroneous processing element, the erroneous processing element signals detection of the correctable error to another processing element, to control the other processing element to delay processing to maintain a predetermined time offset between the erroneous processing element and the other processing element.