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公开(公告)号:US20250117252A1
公开(公告)日:2025-04-10
申请号:US18483636
申请日:2023-10-10
Applicant: Arm Limited
Inventor: Kim Richard SCHUTTENBERG , Joshua David KNEBEL
Abstract: Apparatuses, methods, systems, chip containing products, and computer readable media are disclosed. An apparatus comprises dispatch circuitry to receive instructions, and to identify linear chains of instructions each comprising a first instruction and one or more further instructions, which are temporarily ineligible for execution due to a dependence on an immediately preceding instruction. The apparatus further comprises offline storage circuitry. The dispatch circuitry is configured, for each of the linear chains: to dispatch the sequentially first instruction to the issue circuitry and to retain the one or more further instructions in the offline storage circuitry until a chain trigger signal is received, the chain trigger signal indicating that a previously dispatched instruction, on which a sequentially next instruction depends, has satisfied a predefined issuing condition. In response to receipt of the chain trigger signal, the dispatch circuitry is configured to dispatch the sequentially next instruction to the issue circuitry.
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公开(公告)号:US20240111535A1
公开(公告)日:2024-04-04
申请号:US17959556
申请日:2022-10-04
Applicant: Arm Limited
Inventor: William Elton BURKY , Nicholas Andrew PLANTE , Alexander Cole SHULYAK , Joshua David KNEBEL , Yasuo ISHII
CPC classification number: G06F9/30145 , G06F9/30181 , G06F9/3855
Abstract: A data processing apparatus includes detection circuitry that detects a parent instruction and a child instruction from a stream of instructions. The parent instruction references a destination register that is referenced as a source register by the child instruction. Adjustment circuitry then adjusts the child instruction to produce an adjusted child instruction whose behaviour is logically equivalent to a behaviour of executing the parent instruction followed by the child instruction.
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