公开(公告)号：US20210027148A1

公开(公告)日：2021-01-28

申请号：US16518444

申请日：2019-07-22

Applicant: Arm Limited

Inventor： Lingchuan MENG ,  John Wakefield BROTHERS, III ,  Jens OLSON ,  Jared Corey SMOLENS ,  Eric KUNZE ,  Ian Rudolf BRATT

IPC: G06N3/063 ,  H03M7/30

Abstract: A processor arranged to compress neural network activation data comprising an input module for obtaining neural network activation data. The processor also comprises a block creation module arranged to split the neural network activation data into a plurality of blocks; and a metadata generation module for generating metadata associated with at least one of the plurality of blocks. Based on the metadata generated a selection module selects a compression scheme for each of the plurality of blocks, and a compression module for applying the selected compression scheme to the corresponding block to produce compressed neural network activation data. An output module is also provided for outputting the compressed neural network activation data.