公开(公告)号：US20240386939A1

公开(公告)日：2024-11-21

申请号：US18692395

申请日：2022-08-09

Applicant: Arm Limited

Inventor： Lorenzo Di Gregorio

IPC: G11C11/4078 ,  G11C11/4076 ,  G11C11/408

Abstract: There is provided a data processing apparatus comprising: memory access circuitry configured to issue access requests to a memory system: estimation circuitry configured to estimate a statistical cardinality count on memory row addresses accessed by the access requests: and decay circuitry configured to apply an exponential time-based decay during estimation of the statistical cardinality count.

公开(公告)号：US11615022B2

公开(公告)日：2023-03-28

申请号：US16943121

申请日：2020-07-30

Applicant: Arm Limited

Inventor： Lorenzo Di Gregorio ,  Andrew Brookfield Swaine

IPC: G06F12/0811 ,  G06F1/3206 ,  G06F1/3296 ,  G06F12/0815

Abstract: An apparatus is described that has processing circuitry for performing operations, and a communication path employed by the processing circuitry to access a first memory. Switch circuitry, when activated, is connected to the communication path. The processing circuitry issues access commands specifying addresses to be accessed, where each address is mapped to location in a memory system in accordance with a system address map. The memory system comprises at least the first memory and a second memory. When in a particular mode, the processing circuitry performs operations that require access to only a subset of the locations provided in the first memory. The switch circuitry is arranged, whilst the processing circuitry is in the particular mode, to be activated in order to intercept the access commands issued over the communication path that specify addresses mapped by the system address map to locations within the subset of locations. Those intercepted access commands are redirected to locations within the second memory that are otherwise unused whilst the processing circuitry is in the particular mode. This can provide significant power consumption benefits.