公开(公告)号：US20220188038A1

公开(公告)日：2022-06-16

申请号：US17643732

申请日：2021-12-10

Applicant: Arm Limited

Inventor： Graeme Leslie INGRAM ,  Michael Jean SOLE ,  Erik PERSSON

IPC: G06F3/06 ,  G06F12/10

Abstract: A method for triggering prefetching of memory address translations for memory access requests to be issued by a memory access component of a processor in a data processing system to a memory management function in the data processing system is provided. The method includes obtaining command data from one or more memory access commands in a sequence of memory access commands for the memory access component, predicting one or more memory addresses, for which one or more memory address translations are likely to be required by the memory management function to process one or more memory access requests, from the obtained command data, in response to the predicting, performing one or more trigger operations to trigger a prefetch of the one or more memory address translations, using the predicted one or more memory addresses, in advance of the one or more memory access requests.

公开(公告)号：US20230289185A1

公开(公告)日：2023-09-14

申请号：US18178123

申请日：2023-03-03

Applicant: Arm Limited

Inventor： Michael Jean SOLE ,  Cedric Denis Robert AIRAUD

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3836

Abstract: A data processing apparatus comprises processing circuitry to execute processing instructions, the processing circuitry comprising: a set of physical registers; instruction decoder circuitry to decode processing instructions; detector circuitry to detect groups of instructions which comply with a conflict condition, in which a group of instructions complies with the conflict condition at least when a given storage element is written to by a maximum of one instruction of that group of instructions; instruction issue circuitry to issue decoded instructions for execution; and instruction execution circuitry to execute instructions decoded by the instruction decoder circuitry.