公开(公告)号：US11157277B2

公开(公告)日：2021-10-26

申请号：US16561430

申请日：2019-09-05

Applicant: Arm Limited

Inventor： Cedric Denis Robert Airaud ,  Albin Pierrick Tonnerre ,  Luca Nassi ,  Remi Marius Teyssier

IPC: G06F9/30 ,  G06F9/38

Abstract: Data processing apparatus comprises a processing element configured to access an architectural register representing a given system register; mapping circuitry to map the architectural register representing the given system register to a physical register selected from a set of physical registers; a register bank having a set of two or more respective banked versions of the given system register, in which a respective one of the banked versions of the system register is associated with each of a plurality of current operating states of the processing element; in which, when the processing element changes operating state from a first operating state associated with a first one of the banked versions of the system register to a second operating state associated with a second, different, one of the banked versions of the system register, the processing element is configured to store the current contents of the architectural register representing the given system register to the first one of the banked versions of the system register and to copy the contents of the second one of the banked versions of the system register to the architectural register representing the given system register.

公开(公告)号：US10915327B2

公开(公告)日：2021-02-09

申请号：US16220050

申请日：2018-12-14

Applicant: Arm Limited

Inventor： Luca Nassi ,  Remi Marius Teyssier ,  François Donati ,  Damian Maiorano

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48

Abstract: Aspects of the present disclosure relate to an apparatus comprising a plurality of clusters, each cluster having a plurality of execution units to execute instructions. The apparatus comprises dispatch circuitry to determine, for each instruction to be executed, a chosen cluster from amongst the plurality of clusters to which to dispatch that instruction for execution. This determination is performed by selecting between a default dispatch policy wherein said chosen cluster is a cluster to which an earlier instruction to generate at least one source operand of said instruction was dispatched for execution, and an alternative dispatch policy for selecting said chosen cluster. Said selecting is based on a selection parameter. The dispatch circuitry is further configured to dispatch said instruction to the chosen cluster for execution.

公开(公告)号：US10977044B2

公开(公告)日：2021-04-13

申请号：US16561383

申请日：2019-09-05

Applicant: Arm Limited

Inventor： Remi Marius Teyssier ,  Luca Nassi ,  Albin Pierrick Tonnerre ,  François Donati

IPC: G06F9/38 ,  G06F9/30 ,  G06F21/55

Abstract: An apparatus comprising processing circuitry is provided, the processing circuitry comprising execution circuitry, commit circuitry, issue circuitry comprising an issue queue and selection circuitry, and a branch predictor. The processing circuitry is configured to identify a speculation barrier instruction in the commit queue. While an entry in the commit queue identifies a speculation barrier instruction, when a branch instruction that follows the speculation barrier instruction in the program order is selected for issue, the processing circuitry performs a first execution of the instruction, inhibiting updating of branch prediction data items associated with the branch instruction and inhibiting the selection circuitry from invalidating the associated issue queue entry. When the speculation barrier instruction completes, the processing circuitry is configured to perform a second execution of the instruction, updating the branch prediction data items associated with the branch instruction and allowing the issue circuitry to invalidate the associated issue queue entry.