公开(公告)号：US20240070064A1

公开(公告)日：2024-02-29

申请号：US17893342

申请日：2022-08-23

Applicant: Arm Limited

Inventor： Richard Jared COOPER

IPC: G06F12/02

CPC classification number: G06F12/0292 ,  G06F2212/7201

Abstract: Circuitry comprises memory address translation circuitry to access memory circuitry storing translation information defining memory address translations from input memory addresses to respective output memory addresses; in which the translation information stored by the memory circuitry comprises a hierarchy of page table levels from a highest page table level to a lowest page table level, each page table level having one or more level tables each comprising two or more entries, in which an entry of a level table at a page table level other than a last page table level of the hierarchy points to a level table at a next lower page table level in the hierarchy; the memory address translation circuitry being configured to select an entry of a level table at each page table level according to a selection value, the selection value being dependent upon a portion, applicable to that page table level, of a given input memory address; in which the memory circuitry is configured to store entries as groups of entries, a group of entries being accessible by a single memory retrieval operation; and in which, for at least a subset of the page table levels, a group of entries stored by the memory circuitry comprises a set of entries from two or more respective level tables.