公开(公告)号：US11249908B1

公开(公告)日：2022-02-15

申请号：US17023771

申请日：2020-09-17

Applicant: Arm Limited

Inventor： Ole Henrik Jahren ,  Ian Rudolf Bratt ,  Sigurd Røed Scheistrøen

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0891 ,  G06F9/30 ,  G06F9/54 ,  G06F12/02

Abstract: An apparatus and method are disclosed for managing cache coherency. The apparatus has a plurality of agents with cache storage for caching data, and coherency control circuitry for acting as a point of coherency for the data by implementing a cache coherency protocol. In accordance with the cache coherency protocol the coherency control circuitry responds to certain coherency events by issuing coherency messages to one or more of the agents. A given agent is arranged, prior to entering a given state in which its cache storage is unused, to perform a flush operation in respect of its cache storage that may cause one or more evict messages to be issued to the coherency control circuitry. Further, once all evict messages resulting from performance of the flush operation has been issued, the given agent issues an evict barrier message to the coherency control circuitry. The apparatus ensures that the evict barrier message is only processed by the coherency control circuitry once all evict messages resulting from performance of the flush operation have been processed by the coherency control circuitry. When processing the evict barrier message, the coherency control circuitry issues a barrier response message to the given agent once it is determined that there are no outstanding coherency messages, and the given agent defers entering the given state until at least the barrier response message is received.