公开(公告)号：US20200310796A1

公开(公告)日：2020-10-01

申请号：US16368930

申请日：2019-03-29

Applicant: Arm Limited

Inventor： Nicholas Andrew PFISTER ,  Srinivas VEMURI ,  David Raymond LUTZ

IPC: G06F9/30

Abstract: An apparatus has processing circuitry to perform, in response to decoding of an iterative-operation instruction by the instruction decoder, an iterative operation comprising at least two iterations of processing where one iteration depends on an operand generated in a previous iteration. Preliminary information generating circuitry performs a preliminary portion of processing for a given iteration to generate preliminary information. Result generating circuitry performs a remaining portion of processing for the given iteration, to generate a result value using the preliminary information. Forwarding circuitry forwards the result value as an operand for a next iteration of the iterative operation, for iterations other than the final iteration. The preliminary information generating circuitry starts performing the preliminary portion for the next iteration in parallel with the result generating circuitry completing the remaining portion for the current iteration, to improve performance.