公开(公告)号：US20230120783A1

公开(公告)日：2023-04-20

申请号：US17905225

申请日：2020-12-21

Applicant: ARM LIMITED

Inventor： Mbou EYOLE ,  Michiel Willem VAN TOL ,  Stefanos KAXIRAS

IPC: G06F9/38

Abstract: Apparatuses and methods are provided, relating to the control of data processing in devices which comprise both decoupled access-execute processing circuitry and prefetch circuitry. Control of the access portion of the decoupled access-execute processing circuitry may be dependent on a performance metric of the prefetch circuitry. Alternatively or in addition, control of the prefetch circuitry may be dependent on a performance metric of the access portion.

公开(公告)号：US20220391214A1

公开(公告)日：2022-12-08

申请号：US17755130

申请日：2020-10-15

Applicant: Arm Limited

Inventor： Mbou EYOLE ,  Stefanos KAXIRAS

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus comprises first instruction execution circuitry, second instruction execution circuitry, and a decoupled access buffer. Instructions of an ordered sequence of instructions are issued to one of the first and second instruction execution circuitry for execution in dependence on whether the instruction has a first type label or a second type label. An instruction with the first type label is an access-related instruction which determines at least one characteristic of a load operation to retrieve a data value from a memory address. Instruction execution by the first instruction execution circuitry of instructions having the first type label is prioritised over instruction execution by the second instruction execution circuitry of instructions having the second type label. Data values retrieved from memory as a result of execution of the first type instructions are stored in the decoupled access buffer.

公开(公告)号：US20220391101A1

公开(公告)日：2022-12-08

申请号：US17755133

申请日：2020-10-07

Applicant: ARM LIMITED

Inventor： Mbou EYOLE ,  Stefanos KAXIRAS

IPC: G06F3/06

Abstract: When load requests are generated to support data processing operations, the load requests are buffered in pending load buffer circuitry prior to being carried out. Coalescing circuitry determines for a first load request whether a set of one or more subsequent load requests buffered in the pending load buffer circuitry satisfies an address proximity condition. The address proximity condition is satisfied when all data items identified by the set of one or more subsequent load requests are comprised within a series of data items which will be retrieved from the memory system in response to the first load request. When the address proximity condition is satisfied, forwarding of the set of one or more subsequent load requests is suppressed.