公开(公告)号：US10942870B1

公开(公告)日：2021-03-09

申请号：US16578571

申请日：2019-09-23

Applicant: Arm Limited

Inventor： Yongkang Liu ,  Zhenzhen Zhu

IPC: G06F3/06 ,  G06F12/14 ,  G06F13/18

Abstract: Circuitry comprises memory access control circuitry responsive to initiation of a memory access transaction relating to a given memory address, the memory access transaction being initiated in an access mode selected from at least a higher access mode and a lower access mode, the higher access mode having a higher access level than the lower access mode such that memory access transactions in the lower access mode are inhibited from accessing at least some processing resources associated with memory access transactions in the higher access mode, the memory access control circuitry comprising: circuitry to access permission data associated with candidate memory addresses to be accessed; detector circuitry to detect, for a memory access transaction initiated in the lower access mode, whether the permission data associated with the given memory address indicates an upgraded access mode; and transaction modifier circuitry to associate with the memory access transaction an indication that the memory access transaction may proceed in the higher access mode, when the detector circuitry detects that the permission data associated with the given memory address indicates an upgraded access mode.

公开(公告)号：US20210089473A1

公开(公告)日：2021-03-25

申请号：US16578571

申请日：2019-09-23

Applicant: Arm Limited

Inventor： Yongkang LIU ,  Zhenzhen Zhu

IPC: G06F12/14 ,  G06F13/18

Abstract: Circuitry comprises memory access control circuitry responsive to initiation of a memory access transaction relating to a given memory address, the memory access transaction being initiated in an access mode selected from at least a higher access mode and a lower access mode, the higher access mode having a higher access level than the lower access mode such that memory access transactions in the lower access mode are inhibited from accessing at least some processing resources associated with memory access transactions in the higher access mode, the memory access control circuitry comprising: circuitry to access permission data associated with candidate memory addresses to be accessed; detector circuitry to detect, for a memory access transaction initiated in the lower access mode, whether the permission data associated with the given memory address indicates an upgraded access mode; and transaction modifier circuitry to associate with the memory access transaction an indication that the memory access transaction may proceed in the higher access mode, when the detector circuitry detects that the permission data associated with the given memory address indicates an upgraded access mode.