公开(公告)号：US07069372B1

公开(公告)日：2006-06-27

申请号：US10177187

申请日：2002-06-20

申请人： Arthur Leung, Jr. ,  Anthony J. Li ,  William L. Lynch ,  Sharad Mehrotra

发明人： Arthur Leung, Jr. ,  Anthony J. Li ,  William L. Lynch ,  Sharad Mehrotra

IPC分类号： G06F1/00

CPC分类号： G06F9/3867 ,  G06F9/3802 ,  G06F15/8046 ,  H04L45/60 ,  H04L49/3009

摘要： A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of programmable functional units and register files arranged sequentially as stages, for processing packet contexts (which contain the packet's destination address) to perform operations, under programmatic control, to determine the destination port of the router for the packet. A single stage of the systolic array may contain a register file and one or more functional units such as adders, shifters, logical units, etc., for performing, in one example, very long instruction word (vliw) operations. The processor may also include a forwarding table memory, on-chip, for storing routing information, and a cross bar selectively connecting the stages of the systolic array with the forwarding table memory.

摘要翻译： 一种用于路由器的处理器，所述处理器具有用于处理数据分组的收缩阵列流水线，以确定路由器的哪个输出端口应该路由数据分组。 在一个实施例中，收缩阵列管线包括多个可编程功能单元和按顺序排列的寄存器文件，用于在程序化控制下处理分组上下文（其包含分组的目的地地址）以执行操作，以确定目标端口 路由器为数据包。 收缩阵列的单级可以包含寄存器文件和一个或多个功能单元，例如加法器，移位器，逻辑单元等，用于在一个示例中执行非常长的指令字（vliw）操作。 处理器还可以包括用于存储路由信息的片上转发表存储器，以及选择性地将收缩阵列的级与转发表存储器连接的交叉条。