公开(公告)号：US20200379931A1

公开(公告)日：2020-12-03

申请号：US16947937

申请日：2020-08-25

Applicant: Atmel Corporation

Inventor： Guillaume Pean ,  Vincent Debout ,  Marc Maunier

IPC: G06F13/20 ,  G06F13/10 ,  G06F13/40

Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.

公开(公告)号：US11809346B2

公开(公告)日：2023-11-07

申请号：US16947937

申请日：2020-08-25

Applicant: Atmel Corporation

Inventor： Guillaume Pean ,  Vincent Debout ,  Marc Maunier

IPC: G06F13/20 ,  G06F13/10 ,  G06F13/40

CPC classification number: G06F13/20 ,  G06F13/102 ,  G06F13/4068

Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.

公开(公告)号：US10776294B2

公开(公告)日：2020-09-15

申请号：US14942713

申请日：2015-11-16

Applicant: Atmel Corporation

Inventor： Guillaume Pean ,  Vincent Debout ,  Marc Maunier

IPC: G06F13/20 ,  G06F13/10 ,  G06F13/40

Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.