公开(公告)号：US11443709B2

公开(公告)日：2022-09-13

申请号：US17394382

申请日：2021-08-04

申请人： Au Optronics Corporation

发明人： Che-Wei Tung ,  Wei-Li Lin ,  Chin-Hsien Chou ,  Yen-Wei Yeh

IPC分类号： G09G3/36

摘要： A display panel is provided. The display panel includes a plurality of scan lines and a gate driving circuit. The scan lines are disposed on the display panel along a first direction, and respectively provide a plurality of gate driving signals. The gate driving circuit is disposed on a first side of the display panel along a second direction. The second direction intersects the first direction. The gate driving circuit includes a plurality of bias generators and a plurality of signal output circuits. The signal output circuits are divided into a plurality of groups. The bias generators respectively correspond to the groups. The bias generators generate a plurality of first bias voltages. The groups generate the gate driving signals respectively according to the first bias voltages.

公开(公告)号：US20220215809A1

公开(公告)日：2022-07-07

申请号：US17394382

申请日：2021-08-04

申请人： Au Optronics Corporation

发明人： Che-Wei Tung ,  Wei-Li Lin ,  Chin-Hsien Chou ,  Yen-Wei Yeh

IPC分类号： G09G3/36

摘要： A display panel is provided. The display panel includes a plurality of scan lines and a gate driving circuit. The scan lines are disposed on the display panel along a first direction, and respectively provide a plurality of gate driving signals. The gate driving circuit is disposed on a first side of the display panel along a second direction. The second direction intersects the first direction. The gate driving circuit includes a plurality of bias generators and a plurality of signal output circuits. The signal output circuits are divided into a plurality of groups. The bias generators respectively correspond to the groups. The bias generators generate a plurality of first bias voltages. The groups generate the gate driving signals respectively according to the first bias voltages.

公开(公告)号：US11158227B2

公开(公告)日：2021-10-26

申请号：US16944547

申请日：2020-07-31

申请人： AU OPTRONICS CORPORATION

发明人： Yen-Wei Yeh ,  Chin-Hsien Chou ,  Wei-Li Lin

IPC分类号： G09G3/20

摘要： A wire component includes a plurality of working signal lines and a plurality of transmitting lines. The working signal lines are configured to respectively provide a plurality of working signals to a driving circuit, and phases of the working signals at least partially lag each other sequentially. The transmitting lines are configured to respectively transmit the working signals, and a portion of the transmitting lines crosses the working signal lines. A first working signal line is configured to provide a first working signal; a second working signal line is configured to provide a second working signal; the first working signal immediately lags the second working signal, and the first working signal line and the second working signal line are arranged with another working signal line therebetween.