公开(公告)号：US11379306B1

公开(公告)日：2022-07-05

申请号：US17388690

申请日：2021-07-29

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Jason F. Ross ,  John Foster ,  David M. Hutcheson

IPC: G06F11/00 ,  G06F11/10 ,  H03M13/29 ,  G11C11/4096 ,  G11C11/419 ,  G11C11/418 ,  G01R31/3177

Abstract: A method for radiation hardening synchronous Dynamic Random Access Memory (DRAM), where Error Detection And Correction (EDAC) is implemented on-chip. Each bank includes a plurality of interleaved single chip Static Random Access Memory (SRAM) cells with bit registers configured to interface with the interleaved SRAM cells. A first column multiplexer (MUX) configured to select which bit register is accessed. A second column multiplexer is configured to select an accessed byte with the WRITE burst or a READ burst from the selected bit registers of the first column multiplexer. EDAC logic is configured to check Error Correction Code (ECC) during a READ burst and generate ECC during an WRITE burst for SRAM writeback during a PRECHARGE command.