公开(公告)号：US20200382105A1

公开(公告)日：2020-12-03

申请号：US16425234

申请日：2019-05-29

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Bradley R. Alford, Jr. ,  Nathan R. Broyer ,  Greg M. Fehling ,  Hock J. Lee ,  Jeffrey P. Woodward ,  John Cummings

IPC: H03H17/06

Abstract: A digital signal processor is designed to channelize an input signal, and includes a channelizer circuit and a plurality of tuning modules. The channelizer circuit is designed to receive an input signal having a first bandwidth and to channelize the input signal into a first set of channels each having a bandwidth smaller than the first bandwidth as a first output signal and to channelize the input signal into a second set of channels having a bandwidth smaller than the first bandwidth as a second output signal. The plurality of tuning modules are designed to receive one or more channels from the first output signal or the second output signal and to further downsample the one or more channels to a user-defined bandwidth at a user-defined center frequency. Each of the plurality of tuning modules include a plurality of FIR filter blocks and a memory having a plurality of FIR filter coefficients.

公开(公告)号：US11108381B2

公开(公告)日：2021-08-31

申请号：US16425234

申请日：2019-05-29

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Bradley R. Alford ,  Nathan R. Broyer ,  Greg M. Fehling ,  Hock J. Lee ,  Jeffrey P. Woodward ,  John Cummings

IPC: H03H17/06 ,  H03H17/00

Abstract: A digital signal processor is designed to channelize an input signal, and includes a channelizer circuit and a plurality of tuning modules. The channelizer circuit is designed to receive an input signal having a first bandwidth and to channelize the input signal into a first set of channels each having a bandwidth smaller than the first bandwidth as a first output signal and to channelize the input signal into a second set of channels having a bandwidth smaller than the first bandwidth as a second output signal. The plurality of tuning modules are designed to receive one or more channels from the first output signal or the second output signal and to further downsample the one or more channels to a user-defined bandwidth at a user-defined center frequency. Each of the plurality of tuning modules include a plurality of FIR filter blocks and a memory having a plurality of FIR filter coefficients.