公开(公告)号：US20140372383A1

公开(公告)日：2014-12-18

申请号：US13921089

申请日：2013-06-18

Applicant: BARRACUDA NETWORKS, INC.

Inventor： Josef Sipek

IPC: G06F17/30

CPC classification number: G06F17/30073 ,  G06F3/0658 ,  G06F17/30159

Abstract: A file shard store includes high performance encoding and compaction circuits. An apparatus and its method of operation avoids duplicate storage of file fragments. A plurality of tables control write operations into a plurality of log segments. Shard keys are transferred to uniquely identify fragments of files which may have been previously stored and associated with one or more of client subscribers. An apparatus comprises a plurality of location/subscription tables, a shard transfer circuit, a storage control circuit, an append-to-log circuit coupled to a large storage array, and a log segment compactor circuit.

Abstract translation: 文件分片存储包括高性能编码和压缩电路。 一种装置及其操作方法避免了文件片段的重复存储。 多个表将写入操作控制成多个日志段。 传送碎片密钥以唯一标识可能已经存储并与一个或多个客户端订户相关联的文件片段。 一种装置包括多个位置/订阅表，分片传送电路，存储控制电路，耦合到大存储阵列的附加到对数电路以及对数分段压缩器电路。

公开(公告)号：US09195668B2

公开(公告)日：2015-11-24

申请号：US13921089

申请日：2013-06-18

Applicant: BARRACUDA NETWORKS, INC.

Inventor： Josef Sipek

IPC: G06F17/30

CPC classification number: G06F17/30073 ,  G06F3/0658 ,  G06F17/30159

Abstract: A file shard store includes high performance encoding and compaction circuits. An apparatus and its method of operation avoids duplicate storage of file fragments. A plurality of tables control write operations into a plurality of log segments. Shard keys are transferred to uniquely identify fragments of files which may have been previously stored and associated with one or more of client subscribers. An apparatus comprises a plurality of location/subscription tables, a shard transfer circuit, a storage control circuit, an append-to-log circuit coupled to a large storage array, and a log segment compactor circuit.

Abstract translation: 文件分片存储包括高性能编码和压缩电路。 一种装置及其操作方法避免了文件片段的重复存储。 多个表将写入操作控制成多个日志段。 传送碎片密钥以唯一标识可能已经存储并与一个或多个客户端订户相关联的文件片段。 一种装置包括多个位置/订阅表，分片传送电路，存储控制电路，耦合到大存储阵列的附加到对数电路以及对数分段压缩器电路。