Abstract:
A means of synchronizing clocks without addressing within a cooperative collision avoidance system which utilizes the time slot of the aircraft requesting synchronization. During its time slot, an aircraft transmitting a collision avoidance message automatically requests clock synchronization. All other aircraft within the collision avoidance network which receive the synchronization request will respond in a random manner with a probability inversely proportional to the number of potential responding aircraft within the collision avoidance network. To accomplish this each cooperating aircraft is equipped to monitor the number of occupied time slots so as to determine the number of potential responding aircraft, determines the probability of its response with respect thereto and determines in accordance with the probability thus derived whether it should respond to this particular synchronization request.
Abstract:
Apparatus for synchronizing clocks within a cooperative collision avoidance network wherein an aircraft after operating in an isolated environment for a predetermined time sets its clock in a standby position and listens for start of epoch signals. Upon hearing a start of epoch signal the aircraft immediately starts its clock and begins counting epochs and the time slots contained therein. During own time slot, as determined by its clock, the aircraft transmits a clock synchronization request. If no synchronization responses are received the aircraft will automatically advance its clock by a predetermined amount and once again transmit a synchronization request during its next time slot. If a synchronization response is now received the aircraft will synchronize its clock taking into account the amount of time by which its clock had to be advanced in order to receive the synchronization response. If no response is received the aircraft automatically returns its clock to the standby condition.
Abstract:
A binary pseudo-random frequency generator in which a shift register is continuously strobed by a clock and has its informational content altered in accordance with its acquired state. A variable count divider counts down to zero from a number set therein from information received from the shift register at the divider zero count in response to frequency signals received from a voltage controlled oscillator. Divider zero counts are also compared in a phased lock loop with a reference frequency to set the voltage controlled oscillator frequency.